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Message-ID: <2de0a6e1-0946-4d4f-8e57-1406a437b94e@lunn.ch>
Date: Mon, 10 Jul 2023 23:20:32 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Stefan Eichenberger <eichest@...il.com>
Cc: netdev@...r.kernel.org, hkallweit1@...il.com, linux@...linux.org.uk,
francesco.dolcini@...adex.com, davem@...emloft.net,
edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com
Subject: Re: [PATCH net-next v2 4/4] net: phy: marvell-88q2xxx: add driver
for the Marvell 88Q2110 PHY
> +static int mv88q2xxx_soft_reset(struct phy_device *phydev)
> +{
> + return phy_write_mmd(phydev, MDIO_MMD_PCS,
> + MDIO_PCS_1000BT1_CTRL, MDIO_PCS_1000BT1_CTRL_RESET);
> +}
Does this bit clear on its own when the reset has completed? When
performing a C22 soft reset, the code polls waiting for the bit to
clear. Otherwise there is a danger you start writing other registers
while it is still resetting.
> +static int mv88q2xxx_read_link(struct phy_device *phydev)
> +{
> + u16 ret1, ret2;
> +
> + /* The 88Q2XXX PHYs do not have the PMA/PMD status register available,
> + * therefore we need to read the link status from the vendor specific
> + * registers.
> + */
> + if (phydev->speed == SPEED_1000) {
> + /* Read twice to clear the latched status */
> + ret1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_STAT);
> + ret1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_STAT);
This is generally wrong. See for example genphy_update_link() and
genphy_c45_read_link().
> +static int mv88q2xxx_probe(struct phy_device *phydev)
> +{
> + return 0;
> +}
If it does nothing, it should not be needed.
Andrew
---
pw-bot: cr
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