netdev - RE: [PATCH net-next 2/7] net: pcs: xpcs: support to switch mode for Wangxun NICs

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Date: Wed, 26 Jul 2023 10:40:32 +0800
From: Jiawen Wu <jiawenwu@...stnetic.com>
To: "'Andrew Lunn'" <andrew@...n.ch>
Cc: <netdev@...r.kernel.org>,
	<hkallweit1@...il.com>,
	<linux@...linux.org.uk>,
	<Jose.Abreu@...opsys.com>,
	<mengyuanlou@...-swift.com>
Subject: RE: [PATCH net-next 2/7] net: pcs: xpcs: support to switch mode for Wangxun NICs

On Wednesday, July 26, 2023 1:32 AM, Andrew Lunn wrote:
> > +static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)
> > +{
> > +	int val;
> > +
> > +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);
> > +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);
> > +	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
> > +	val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);
> > +	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
> > +	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, 0xCF00);
> > +	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);
> > +	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x29);
> > +	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0);
> > +	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0);
> > +	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, 0x300);
> > +	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, 0x300);
> > +	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, 0x600);
> > +
> > +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, 0x45);
> > +	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
> > +	val &= ~TXGBE_RX_EQ_ATTN_LVL0;
> > +	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
> > +	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);
> 
> You have a lot of magic numbers above. Please truy to add some
> #defines to try to explain what is going on here.

Some registers give only magic numbers in the fields, like a frequency,
bandwidth, etc. And other fields are reserved. Those registers don't
make much sense to define the bits field. But I'll try to add more
useful defines.