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Message-ID: <1691387509-2113129-5-git-send-email-radhey.shyam.pandey@amd.com> Date: Mon, 7 Aug 2023 11:21:43 +0530 From: Radhey Shyam Pandey <radhey.shyam.pandey@....com> To: <vkoul@...nel.org>, <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>, <michal.simek@....com>, <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>, <linux@...linux.org.uk> CC: <dmaengine@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>, <git@....com>, Radhey Shyam Pandey <radhey.shyam.pandey@....com> Subject: [PATCH net-next v5 04/10] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Increase AXI DMA transaction segments count to ensure that even in high load we always get a free segment in prepare descriptor for a DMA_SLAVE transaction. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com> --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Switch to amd.com email address. --- drivers/dma/xilinx/xilinx_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index d526e472b905..7f3c57fbe1e3 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -178,7 +178,7 @@ #define XILINX_DMA_BD_SOP BIT(27) #define XILINX_DMA_BD_EOP BIT(26) #define XILINX_DMA_COALESCE_MAX 255 -#define XILINX_DMA_NUM_DESCS 255 +#define XILINX_DMA_NUM_DESCS 512 #define XILINX_DMA_NUM_APP_WORDS 5 /* AXI CDMA Specific Registers/Offsets */ -- 2.34.1
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