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Message-ID: <3ocnhpal77jmsqabcmnvekk4sqgookk5sunrvb3hstaupqfaj2@whnb7uj6w7ue> Date: Mon, 7 Aug 2023 16:18:21 -0500 From: Andrew Halaney <ahalaney@...hat.com> To: Bartosz Golaszewski <brgl@...ev.pl> Cc: Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Alex Elder <elder@...aro.org>, Srini Kandagatla <srinivas.kandagatla@...aro.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, netdev@...r.kernel.org, Bartosz Golaszewski <bartosz.golaszewski@...aro.org> Subject: Re: [PATCH 4/9] arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet1 On Mon, Aug 07, 2023 at 09:35:02PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org> > > Add the MDC and MDIO pin functions for ethernet1 on sa8775p-ride. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index 09ae6e153282..38327aff18b0 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -480,6 +480,22 @@ ethernet0_mdio: ethernet0-mdio-pins { > }; > }; > > + ethernet1_default: ethernet1-default-state { > + ethernet1_mdc: ethernet1-mdc-pins { > + pins = "gpio20"; > + function = "emac1_mdc"; > + drive-strength = <16>; > + bias-pull-up; > + }; > + > + ethernet1_mdio: ethernet1-mdio-pins { > + pins = "gpio21"; > + function = "emac1_mdio"; > + drive-strength = <16>; > + bias-pull-up; > + }; > + }; > + With the whole "EMAC0 MDIO handles the ethernet phy for EMAC1", this doesn't seem to make sense. I don't have all the schematics, but these pins are not connected from what I see.
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