netdev - Re: [PATCH net-next] net: dsa: mark parsed interface mode for legacy switch drivers

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Message-ID: <20230813105031.zvagj264hiqvu3xb@skbuf>
Date: Sun, 13 Aug 2023 13:50:31 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
Cc: Linus Walleij <linus.walleij@...aro.org>, Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	netdev@...r.kernel.org
Subject: Re: [PATCH net-next] net: dsa: mark parsed interface mode for legacy
 switch drivers

On Sat, Aug 12, 2023 at 01:16:00PM +0100, Russell King (Oracle) wrote:
> It's actually better - the vitesse driver uses .adjust_link, which
> means it's excluded from phylink for the DSA/CPU ports.
> 
> So, I think for Vitesse, we just need to set INTERNAL and GMII
> for ports != CPU_PORT, speeds 10..1000Mbps at FD and HD, and also
> sym and asym pause.

Ok.

> That leaves the RTL836x driver, for which I've found:
> 
> http://realtek.info/pdf/rtl8366_8369_datasheet_1-1.pdf
> 
> and that indicates that the user ports use RSGMII which is SGMII with
> a clock in one direction. The only dts I can find is:
> 
> arch/arm/boot/dts/gemini-dlink-dir-685.dts
> 
> which doesn't specify phy-mode for these, so that'll be using the
> phylib default of GMII.
> 
> Port 5 supports MII/GMII/RGMII by hardware strapping, which has three
> modes of operation:
> 
>   MII/GMII (mac mode): 1G (GMII) when linked at 1G, otherwise 100M (MII)
>   RGMII: only 1G
>   MII (phy mode): only 100M FD supported. Flow control by hardware
>   strapping but is readable via a register, but omits to say where.
> 
> There's also some suggestion that asym flow control is supported in 1G
> mode - but it doesn't say whether it's supported in 100M (and since
> IEEE 802.3 advertisements do not make this conditional on speed...
> yea, sounds like a slightly broken design to me.)
> 
> So for realtek, I propose (completely untested):
> 
> 8<====
> From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
> Subject: [PATCH net-next] net: dsa: realtek: add phylink_get_caps
>  implementation
> 
> The user ports use RSGMII, but we don't have that, and DT doesn't
> specify a phy interface mode, so phylib defaults to GMII. These support
> 1G, 100M and 10M with flow control. It is unknown whether asymetric
> pause is supported at all speeds.
> 
> The CPU port uses MII/GMII/RGMII/REVMII by hardware pin strapping,
> and support speeds specific to each, with full duplex only supported
> in some modes. Flow control may be supported again by hardware pin
> strapping, and theoretically is readable through a register but no
> information is given in the datasheet for that.
> 
> So, we do a best efforts - and be lenient.
> 
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
> ---
>  drivers/net/dsa/realtek/rtl8366rb.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/net/dsa/realtek/rtl8366rb.c b/drivers/net/dsa/realtek/rtl8366rb.c
> index 25f88022b9e4..76b5c43e1430 100644
> --- a/drivers/net/dsa/realtek/rtl8366rb.c
> +++ b/drivers/net/dsa/realtek/rtl8366rb.c
> @@ -1049,6 +1049,32 @@ static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
>  	return DSA_TAG_PROTO_RTL4_A;
>  }
>  
> +static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
> +				       struct phylink_config *config)
> +{
> +	unsigned long *interfaces = config->supported_interfaces;
> +	struct realtek_priv *priv = ds->priv;
> +
> +	if (port == priv->cpu_port) {
> +		__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
> +		__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
> +		/* Only supports 100M FD */
> +		__set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
> +		/* Only supports 1G FD */
> +		__set_bit(PHY_INTERFACE_MODE_RGMII, interfaces);
> +
> +		config->mac_capabilities = MAC_1000 | MAC_100 |
> +					   MAC_SYM_PAUSE;

Missing "return" statement here.

> +	}
> +
> +	/* RSGMII port, but we don't have that, and we don't
> +	 * specify in DT, so phylib uses the default of GMII
> +	 */
> +	__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
> +	config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
> +				   MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> +}
> +
>  static void
>  rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
>  		      phy_interface_t interface, struct phy_device *phydev,
> @@ -1796,6 +1822,7 @@ static int rtl8366rb_detect(struct realtek_priv *priv)
>  static const struct dsa_switch_ops rtl8366rb_switch_ops_smi = {
>  	.get_tag_protocol = rtl8366_get_tag_protocol,
>  	.setup = rtl8366rb_setup,
> +	.phylink_get_caps = rtl8366rb_phylink_get_caps,
>  	.phylink_mac_link_up = rtl8366rb_mac_link_up,
>  	.phylink_mac_link_down = rtl8366rb_mac_link_down,
>  	.get_strings = rtl8366_get_strings,
> @@ -1821,6 +1848,7 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops_mdio = {
>  	.setup = rtl8366rb_setup,
>  	.phy_read = rtl8366rb_dsa_phy_read,
>  	.phy_write = rtl8366rb_dsa_phy_write,
> +	.phylink_get_caps = rtl8366rb_phylink_get_caps,
>  	.phylink_mac_link_up = rtl8366rb_mac_link_up,
>  	.phylink_mac_link_down = rtl8366rb_mac_link_down,
>  	.get_strings = rtl8366_get_strings,
> -- 
> 2.30.2
> 
> 
> -- 
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!