netdev - Re: [PATCH net-next] net: dsa: realtek: add phylink_get

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Message-ID: <CACRpkdaeds3vP4JBFTcf6zjcNZBnmaCFUF6teYaHDZoJ5ALioA@mail.gmail.com>
Date: Sat, 19 Aug 2023 16:33:37 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, 
	Alvin __ipraga <alsi@...g-olufsen.dk>, Florian Fainelli <f.fainelli@...il.com>, 
	Vladimir Oltean <olteanv@...il.com>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	netdev@...r.kernel.org
Subject: Re: [PATCH net-next] net: dsa: realtek: add phylink_get_caps implementation

On Sat, Aug 19, 2023 at 1:11 PM Russell King (Oracle)
<rmk+kernel@...linux.org.uk> wrote:

> The user ports use RSGMII, but we don't have that, and DT doesn't
> specify a phy interface mode, so phylib defaults to GMII. These support
> 1G, 100M and 10M with flow control. It is unknown whether asymetric
> pause is supported at all speeds.
>
> The CPU port uses MII/GMII/RGMII/REVMII by hardware pin strapping,
> and support speeds specific to each, with full duplex only supported
> in some modes. Flow control may be supported again by hardware pin
> strapping, and theoretically is readable through a register but no
> information is given in the datasheet for that.
>
> So, we do a best efforts - and be lenient.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>

Looks good to me!
Also tested it with an additional patch in the earlier version.
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij