netdev - RE: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code

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Message-ID: <6d35d56f78b7452b9330c3257748fa3c@realtek.com>
Date: Mon, 21 Aug 2023 05:31:09 +0000
From: Justin Lai <justinlai0215@...ltek.com>
To: Andrew Lunn <andrew@...n.ch>
CC: "kuba@...nel.org" <kuba@...nel.org>,
        "davem@...emloft.net"
	<davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>,
        "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>
Subject: RE: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code

> > > Is the 'line' speed of the MAC fixed? It operates at one speed, and that is
> it?
> >
> > Hi, Andrew
> >
> 
> > The "line" speed of the MAC is fixed 5G, but the throughput will be
> > determined according to the speed of the PCIe link. For example, if
> > the link speed is gen 3, the throughput will be 5G. if the link speed
> > is gen 2, the throughput will be 2.5G. if the link speed is gen 1, the
> > throughput will be 1G.
> 
> ksettings does not return throughput, it returns the line speed. throughput is
> determined by a lot of different things, can the CPU handle frames fast enough,
> is the memory bandwidth high enough, what is happening on other ports of
> the PCIe switch etc.
> 
> There is at least one driver i know of which reports a warning at probe time, if
> it finds the device is on a bus which cannot support the full bandwidth. Maybe
> copy that.
> 

Hi, Andrew

Thanks for your guidance, we have represented the actual connection speed in the next version.

> > There is no extra fields in DMA descriptors for tagging protocol. The
> > tag added by switch hardware instead of this driver.
> 
> > > Are the I2C, MDIO and SPI bus masters also hanging off a PCIE
> > > endpoint? Can they probe independently? I'm just want to check this
> > > should not be part of an MFD driver.
> >
> 
> > The I2C, MDIO and SPI bus masters are not hanging off the PCIE
> > endpoints, but on the switch core.
> 
> So the switch core is also an PCIE endpoint?

Sorry, please allow me to explain again.
The RTL90xx Series supports I2C, MDC/MDIO and SPI slave to access the registers of Ethernet Switch Core and the external CPU could manage it via these pins.
You are right, there is a tag protocol in the switch core. But It's for the other ports, usually the cpu port, not this pcie gmac interface.
You can think of this pcie gmac as a NIC connecting to the external ethernet switch directly.

> 
>    Andrew
> .