netdev - Re: [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out

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Date: Fri, 1 Sep 2023 21:45:00 +0530
From: Kathiravan T <quic_kathirav@...cinc.com>
To: Devi Priya <quic_devipriy@...cinc.com>, <andersson@...nel.org>,
        <agross@...nel.org>, <konrad.dybcio@...aro.org>,
        <mturquette@...libre.com>, <sboyd@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <catalin.marinas@....com>, <will@...nel.org>, <p.zabel@...gutronix.de>,
        <richardcochran@...il.com>, <arnd@...db.de>, <geert+renesas@...der.be>,
        <nfraprado@...labora.com>, <rafal@...ecki.pl>, <peng.fan@....com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <netdev@...r.kernel.org>
CC: <quic_saahtoma@...cinc.com>
Subject: Re: [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock


On 8/25/2023 2:42 PM, Devi Priya wrote:
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (nss) clocks.
>
> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> ---
>   drivers/clk/qcom/gcc-ipq9574.c | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 8f430367299e..495a66f7d29a 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -107,6 +107,21 @@ static struct clk_alpha_pll_postdiv gpll0 = {
>   	},
>   };
>   
> +static struct clk_alpha_pll_postdiv gpll0_out_aux = {
> +	.offset = 0x20000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gpll0_out_aux",
> +		.parent_hws = (const struct clk_hw *[]) {
> +			&gpll0_main.clkr.hw
> +		},
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,


You might need to drop the member 'flags '. Please refer 
https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/

I will send the patch to drop the flags in the existing driver sometime 
next week.

Thanks,


> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +	},
> +};
> +
>   static struct clk_alpha_pll gpll4_main = {
>   	.offset = 0x22000,
>   	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> @@ -4144,6 +4159,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
>   	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
>   	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
>   	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> +	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
>   };
>   
>   static const struct qcom_reset_map gcc_ipq9574_resets[] = {