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Message-ID: <daabaedb-1943-425e-b5be-73c4f6566121@lunn.ch>
Date: Wed, 13 Sep 2023 01:52:42 +0200
From: Andrew Lunn <andrew@...n.ch>
To: "Hawkins, Nick" <nick.hawkins@....com>
Cc: "christophe.jaillet@...adoo.fr" <christophe.jaillet@...adoo.fr>,
"simon.horman@...igine.com" <simon.horman@...igine.com>,
"Verdun, Jean-Marie" <verdun@....com>,
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"edumazet@...gle.com" <edumazet@...gle.com>,
"kuba@...nel.org" <kuba@...nel.org>,
"pabeni@...hat.com" <pabeni@...hat.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
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"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 4/5] net: hpe: Add GXP UMAC Driver
> Greetings Andrew,
>
> In that case I will continue to attempt to try and adopt the page pool
> API. In all the examples with page pool HW rings it appears they are
> using alloc_etherdev_mqs. Are there any HW requirements to use this
> library? If there are none what is the typical number for rx and tx
> queues?
There are no hardware requirements as far as i understand it. If your
hardware only has one RX queue and one TX queue, define it as
1. Having more allows you to spread the load over multiple CPUs, with
each queue typically having its own interrupt, and interrupts are then
mapped to a single CPU. But if you don't have any of that, it should
not be a hindrance.
Andrew
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