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Message-ID: <169470176101.1248181.5708025774041263558.robh@kernel.org> Date: Thu, 14 Sep 2023 09:29:21 -0500 From: Rob Herring <robh@...nel.org> To: MD Danish Anwar <danishanwar@...com> Cc: Jakub Kicinski <kuba@...nel.org>, Simon Horman <horms@...nel.org>, linux-kernel@...r.kernel.org, Andrew Lunn <andrew@...n.ch>, Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org, Eric Dumazet <edumazet@...gle.com>, Vignesh Raghavendra <vigneshr@...com>, Rob Herring <robh+dt@...nel.org>, "David S. Miller" <davem@...emloft.net>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Roger Quadros <rogerq@...com>, devicetree@...r.kernel.org, srk@...com, r-gunasekaran@...com, Roger Quadros <rogerq@...nel.org> Subject: Re: [PATCH net-next v3 1/2] dt-bindings: net: Add documentation for Half duplex support. On Wed, 13 Sep 2023 14:40:10 +0530, MD Danish Anwar wrote: > In order to support half-duplex operation at 10M and 100M link speeds, the > PHY collision detection signal (COL) should be routed to ICSSG > GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal > and apply the CSMA/CD algorithm applicable for half duplex operation. A DT > property, "ti,half-duplex-capable" is introduced for this purpose. If > board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can > be added to eth node of ICSSG, MII port to support half duplex operation at > that port. > > Reviewed-by: Roger Quadros <rogerq@...nel.org> > Signed-off-by: MD Danish Anwar <danishanwar@...com> > --- > Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > Reviewed-by: Rob Herring <robh@...nel.org>
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