netdev - Re: [PATCH bpf-next v2 5/6] riscv, bpf: Optimize sign-extention mov insns with Zbb support

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Message-ID: <87sf6ymuct.fsf@all.your.base.are.belong.to.us>
Date: Thu, 28 Sep 2023 13:04:50 +0200
From: Björn Töpel <bjorn@...nel.org>
To: Pu Lehui <pulehui@...weicloud.com>, bpf@...r.kernel.org,
 linux-riscv@...ts.infradead.org, netdev@...r.kernel.org
Cc: Alexei Starovoitov <ast@...nel.org>, Daniel Borkmann
 <daniel@...earbox.net>, Andrii Nakryiko <andrii@...nel.org>, Martin KaFai
 Lau <martin.lau@...ux.dev>, Song Liu <song@...nel.org>, Yonghong Song
 <yhs@...com>, John Fastabend <john.fastabend@...il.com>, KP Singh
 <kpsingh@...nel.org>, Stanislav Fomichev <sdf@...gle.com>, Hao Luo
 <haoluo@...gle.com>, Jiri Olsa <jolsa@...nel.org>, Palmer Dabbelt
 <palmer@...belt.com>, Conor Dooley <conor@...nel.org>, Luke Nelson
 <luke.r.nels@...il.com>, Pu Lehui <pulehui@...wei.com>, Pu Lehui
 <pulehui@...weicloud.com>
Subject: Re: [PATCH bpf-next v2 5/6] riscv, bpf: Optimize sign-extention mov
 insns with Zbb support

Pu Lehui <pulehui@...weicloud.com> writes:

> From: Pu Lehui <pulehui@...wei.com>
>
> Add 8-bit and 16-bit sign-extention wraper with Zbb support to optimize
> sign-extension mov instructions.
>
> Signed-off-by: Pu Lehui <pulehui@...wei.com>
> ---
>  arch/riscv/net/bpf_jit.h        | 20 ++++++++++++++++++++
>  arch/riscv/net/bpf_jit_comp64.c |  5 +++--
>  2 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> index 4e24fb2bd..944bdd6e4 100644
> --- a/arch/riscv/net/bpf_jit.h
> +++ b/arch/riscv/net/bpf_jit.h
> @@ -1110,6 +1110,26 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
>  		emit(rv_subw(rd, rs1, rs2), ctx);
>  }
>  
> +static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx)
> +{
> +	if (rvzbb_enabled()) {
> +		emit(rvzbb_sextb(rd, rs), ctx);
> +	} else {
> +		emit_slli(rd, rs, 56, ctx);
> +		emit_srai(rd, rd, 56, ctx);
> +	}
> +}
> +
> +static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
> +{
> +	if (rvzbb_enabled()) {
> +		emit(rvzbb_sexth(rd, rs), ctx);
> +	} else {
> +		emit_slli(rd, rs, 48, ctx);
> +		emit_srai(rd, rd, 48, ctx);
> +	}
> +}

Nit/personal style: I really find it easier to read early-exit code,
than nested if-else.

  | if (cond) {
  |   foo();
  |   return;
  | }
  | 
  | bar();

> +
>  static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
>  {
>  	emit_addiw(rd, rs, 0, ctx);
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index 0c6ffe11a..f4ca6b787 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -1027,9 +1027,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>  			emit_mv(rd, rs, ctx);
>  			break;
>  		case 8:
> +			emit_sextb(rd, rs, ctx);
> +			break;
>  		case 16:
> -			emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx);
> -			emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
> +			emit_sexth(rd, rs, ctx);

Acked-by: Björn Töpel <bjorn@...nel.org>