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Date: Tue, 24 Oct 2023 11:03:05 +0200 (CEST)
From: Romain Gantois <romain.gantois@...tlin.com>
To: Andrew Lunn <andrew@...n.ch>
cc: Romain Gantois <romain.gantois@...tlin.com>, davem@...emloft.net, 
    Rob Herring <robh+dt@...nel.org>, 
    Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, 
    Jakub Kicinski <kuba@...nel.org>, Eric Dumazet <edumazet@...gle.com>, 
    Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org, 
    linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
    thomas.petazzoni@...tlin.com, Florian Fainelli <f.fainelli@...il.com>, 
    Heiner Kallweit <hkallweit1@...il.com>, 
    Russell King <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org, 
    Vladimir Oltean <vladimir.oltean@....com>, 
    Luka Perkov <luka.perkov@...tura.hr>, 
    Robert Marko <robert.marko@...tura.hr>, Andy Gross <agross@...nel.org>, 
    Bjorn Andersson <andersson@...nel.org>, 
    Konrad Dybcio <konrad.dybcio@...ainline.org>, 
    Maxime Chevallier <maxime.chevallier@...tlin.com>
Subject: Re: [PATCH net-next 4/5] net: ipqess: add a PSGMII calibration
 procedure to the IPQESS driver

Hello Andrew,

On Mon, 23 Oct 2023, Andrew Lunn wrote:

> On Mon, Oct 23, 2023 at 05:50:11PM +0200, Romain Gantois wrote:
> > The IPQ4019 Ethernet Switch Subsystem uses a PSGMII link to communicate
> > with a QCA8075 5-port PHY. This 1G link requires calibration before it can
> > be used reliably.
> > 
> > This commit introduces a calibration procedure followed by thourough
> > testing of the link between each switch port and its corresponding PHY
> > port.
> 
> Could you explain the architecture in a bit more detail.
> 
> When i see MAC code messing with a PHY, i normally say move it into
> the PHY driver. But its not clear to me if you are talking about the
> real PHYs here, or this is the switch end of the link, and it has some
> sort of a PHY to talk to the quint PHY?

Yes, I'll add more detailed comments to the code in the v2. The calibration 
procedure itself targets the PSGMII device, which is internal to the SoC and can 
be logically accessed as a PHY device on the MDIO bus. This component is a 
little opaque and has some nonstandard MII register definitions.

The "testing" phase that follows the calibration accesses both the internal 
QCA8K switch ports and the external QCA8075 PHY. For example, it puts both the 
switch ports and the PHY ports in loopback before starting packet generation on 
the external PHYs. This is done to verify that the PSGMII link works correctly 
after being calibrated.

So this code interacts with both internal ESS devices and external PHYs, but 
mostly the former, which is why I kept everything in the MAC/switch driver.

Thanks,

Romain

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