lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Sat, 18 Nov 2023 16:36:54 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Jie Luo <quic_luoj@...cinc.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, agross@...nel.org,
	andersson@...nel.org, konrad.dybcio@...aro.org, davem@...emloft.net,
	edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
	robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
	conor+dt@...nel.org, hkallweit1@...il.com, linux@...linux.org.uk,
	robert.marko@...tura.hr, linux-arm-msm@...r.kernel.org,
	netdev@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, quic_srichara@...cinc.com
Subject: Re: [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332
 platform

> The clock arguments are provided in the later part as below. i will also
> provide more detail clock names for the new added clocks for the ipq5332
> platform in description.
> 
>   - if:
> 
>       properties:
> 
>         compatible:
> 
>           contains:
> 
>             enum:
> 
>               - qcom,ipq5332-mdio
> 
>     then:
> 
>       properties:
> 
>         clocks:
> 
>           items:
> 
>             - description: MDIO clock source frequency fixed to 100MHZ
> 
>             - description: UNIPHY0 AHB clock source frequency fixed to
> 100MHZ
>             - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ
>             - description: UNIPHY1 AHB clock source frequency fixed to
> 100MHZ
>             - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ

As i said before, the frequency of the clocks does not matter
here. That appears to be the drivers problem. I assume every board
design, with any sort of PHY, needs the same clock configuration?

      Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ