netdev - Re: [net-next RFC PATCH 03/14] dt-bindings: net: document ethernet PHY package nodes

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Message-ID: <c697488a-d34c-4c98-b4c7-64aef2fe583f@lunn.ch>
Date: Thu, 23 Nov 2023 15:27:05 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Rob Herring <robh@...nel.org>, "David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>, Andy Gross <agross@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konrad.dybcio@...aro.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	Florian Fainelli <florian.fainelli@...adcom.com>,
	Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
	Daniel Golle <daniel@...rotopia.org>,
	Qingfang Deng <dqfext@...il.com>,
	SkyLake Huang <SkyLake.Huang@...iatek.com>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	David Epping <david.epping@...singlinkelectronics.com>,
	Vladimir Oltean <olteanv@...il.com>,
	"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
	Harini Katakam <harini.katakam@....com>,
	Simon Horman <horms@...nel.org>,
	Robert Marko <robert.marko@...tura.hr>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org
Subject: Re: [net-next RFC PATCH 03/14] dt-bindings: net: document ethernet
 PHY package nodes

> Just to be more precise qca807x can operate in 3 different mode:
> (this is controlled by the MODE_CFG bits)

> - QSGMII: 5 copper port

4 slots over QSGMII, plus the second SERDES is connected to the MAC
using SGMII/1000BaseX?

> - PSGMII: 5 copper port

5 slots over QSGMII, the second SERDES is idle?

> - PSGMII: 4 copper port + 1 combo (that can be both fiber or copper)

5 slots over QSGMII, with the second SERDES connected to an SFP cage.

Are ports 1-4 always connected to the P/Q SGMII. Its only port 5 which
can use the second SERDES?

Does changing between QSGMII and PSGMII really change the protocol run
over the multiplex link? The clock rate is slower, there are only 4
multiplexed slots vs five? Or does it keep using PSGMII and leaves one slot

I can see how it is messy to validate, if you only have phy-mode. So
maybe MODE_CFG is a package property. You then can validate the
phy-mode against MODE_CFG.

	 Andrew