Message-ID: <ff0fb7aa-8985-48f1-8296-1b253625e19d@gmail.com>
Date: Tue, 2 Jan 2024 14:18:53 +0100
From: Heiner Kallweit <hkallweit1@...il.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>,
 Marek Behún <kabel@...nel.org>
Cc: netdev@...r.kernel.org, Andrew Lunn <andrew@...n.ch>,
 "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>, Alexander Couzens <lynxis@...0.eu>,
 Daniel Golle <daniel@...rotopia.org>, Willy Liu <willy.liu@...ltek.com>,
 Ioana Ciornei <ioana.ciornei@....com>, Marek Mojík
 <marek.mojik@....cz>, Maximilián Maliar
 <maximilian.maliar@....cz>
Subject: Re: [PATCH net-next 03/15] net: phy: realtek: rework MMD register
 access methods

On 02.01.2024 12:16, Russell King (Oracle) wrote:
> On Wed, Dec 20, 2023 at 04:55:06PM +0100, Marek Behún wrote:
>> The .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
>> currently allow access to only 6 MMD registers, via a vendor specific
>> mechanism (a paged read / write).
>>
>> The PHY specification explains that MMD registers for MMDs 1 to 30 can
>> be accessed via the clause 22 indirect mechanism through registers 13
>> and 14, but this is not possible for MMD 31.
>>
>> A Realtek contact explained that MMD 31 registers can be accessed by
>> setting clause 22 page register (register 31):
>>   page = mmd_reg >> 4
>>   reg = 0x10 | ((mmd_reg & 0xf) >> 1)
>>
>> This mechanism is currently used in the driver. For example the
>> .read_mmd() method accesses the PCS.EEE_ABLE register by setting page
>> to 0xa5c and accessing register 0x12. By the formulas above, this
>> corresponds to MMD register 31.a5c4. The Realtek contact confirmed that
>> the PCS.EEE_ABLE register (3.0014) is also available via MMD alias
>> 31.a5c4, and this is also true for the other registers:
>>
>>   register name   address   page.reg  alias
>>   PCS.EEE_ABLE    3.0x0014  0xa5c.12  31.0xa5c4
>>   PCS.EEE_ABLE2   3.0x0015  0xa6e.16  31.0xa6ec
>>   AN.EEE_ADV      7.0x003c  0xa5d.10  31.0xa5d0
>>   AN.EEE_LPABLE   7.0x003d  0xa5d.11  31.0xa5d2
>>   AN.EEE_ADV2     7.0x003e  0xa6d.12  31.0xa6d4
>>   AN.EEE_LPABLE2  7.0x003f  0xa6d.10  31.0xa6d0
>>
>> Since the registers are also available at the true MMD addresses where
>> they can be accessed via the indirect mechanism (via registers 13 and
>> 14) we can rework the code to be more generic and allow access to all
>> MMD registers.
>>
Marek and me had a separate communication about the version of these PHY's
used as internal PHY's on RTL8125 MAC/PHY combination.
Depending on the RTL8125 version the PHY's identify as either RTL8226 or
RTL8226B. Problem is that these internal PHY's are crippled and don't
support the indirect MMD access over c22.
In my tests all indirect MMD reads returned 0.
Therefore this patch has to be reworked.

In order not to break handling of the RTL8125-internal PHY's, we have to
keep the access to the vendor-specific registers. What could be done:
Split the PHY driver for e.g. RTL8226B into one for the RTL8125-internal
version and one for the standalone version (using match_phy_device and
maybe using the MMD read result as differentiating criteria).
Then the one for the standalone version could use core c45 functions.

>> Rework the .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
>> PHYs:
>> - use direct clause 45 access if the MDIO bus supports it
>> - use the indirect access via clause 22 registers 13 and 14 for MMDs
>>   1 to 30
>> - use the vendor specific method to access MMD 31 registers
>>
>> Signed-off-by: Marek Behún <kabel@...nel.org>
>> ---
> 
> Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
> 
> Thanks!
> 

Powered by blists - more mailing lists