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Date: Mon, 8 Jan 2024 19:13:34 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>, Sergey Ryazanov <ryazanov.s.a@...il.com>
CC: Christian Marangi <ansuelsmth@...il.com>,
Robert Marko
<robert.marko@...tura.hr>,
Vladimir Oltean <olteanv@...il.com>, Rob Herring
<robh+dt@...nel.org>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet
<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni
<pabeni@...hat.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Andy Gross <agross@...nel.org>,
Bjorn
Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
<netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>
Subject: Re: [net-next PATCH RFC v3 1/8] dt-bindings: net: document ethernet
PHY package nodes
On 1/8/2024 2:31 AM, Andrew Lunn wrote:
>> And I would like to ask you about another issue raised by Vladimir [1].
>> These phy chips become SoC with all these built-in PHYs, PCSs, clocks,
>> interrupt controllers, etc. Should we address this now? Or should we go with
>> the proposed solution for now and postpone modeling of other peripherals
>> until we get a real hardware, as Andrew suggested?
>>
>> I'm asking because it looks like we have got a real hardware. Luo currently
>> trying to push QCA8084 (multi-phy/switch chip) support, and this chip
>> exactly contains a huge clock/reset controller [2,3].
>
> Ideally the reset controller is modelled as a Linux reset
> controller. The clock part of it is modelled using the common clock
> framework. When done correctly, the PHY should not really care. All it
> does is ask for its clock to be enabled, and its reset to be disabled.
>
> Also, given how difficult it is proving to be to make any progress at
> all, i want to get one little part correctly described, the pure
> PHY. Once we have that, we can start on the next little part. So long
> as we keep to the Linux architecture of blocks or hardware with
> standard Linux drivers, and DT to glue them together, a small step by
> step approach should work out.
>
> Andrew
Since qca8075 PHY is also multiple port PHY, which is same as qca8084,
but qca8084 also includes the integrated clock controller, this is the
first qcom PHY chip integrating the clock controller internally.
can we also consider designing the clocks and resets DT models in the
PHY package DT.
For qca8084 PURE PHY chip, which is the quad PHY chip and two PCSes,
it integrates the clock controller that generates the clocks to be used
by the link of PHYs, the integrated controller also provides the resets
to the PHY, the clock controller(NSSCC) driver of qca8084 works at the
same way of the GCC of SoC(IPQ), qca8084 needs to be initialized with
the clocks and resets for the qca8084 PHY package, these clocks and
resets are generated by the NSSCC, even for PURE phy chip qca8084, there
is also some PHY package level clocks needs to be initialized.
here is the diagram of qca8084.
__| |_______________| |__
| PCS0 | |PCS1 |
|______| |_____|
|_________________ |
| | |
| NSSCC | |
|________________| |
|_______________________|
| | | | |
|PHY1 |PHY2 |PHY3 |PHY4 |
|_____|_____|_____|_____|
let me example the initial clocks and resets for the pure PHY chip
qca8084 as below, the clocks and resets should be put into the first
MDIO node to be initialized firstly before qca8084 PHY will work.
ethernet-phy-package@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ethernet-phy-package";
reg = <0>;
/* initial PHY package level clocks */
clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
<&qca8k_nsscc NSS_CC_AHB_CLK>,
<&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
<&qca8k_nsscc NSS_CC_TLMM_CLK>,
<&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
<&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
<&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>;
clock-names = "apb_bridge",
"ahb",
"sec_ctrl_ahb",
"tlmm",
"tlmm_ahb",
"cnoc_ahb",
"mdio_ahb";
/* initial PHY package level reset */
resets = <&qca8k_nsscc NSS_CC_DSP_ARES>;
reset-names = "gephy_dsp";
/* initial clocks and resets for first phy */
phy0 {
reg = <0>;
clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
clock-names = "gephy0_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY0_ARES>;
reset-names = "gephy0_sys",
"gephy0_soft";
};
/* initial clocks and resets for second phy */
phy1 {
reg = <1>;
clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
clock-names = "gephy1_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY1_ARES>;
reset-names = "gephy1_sys",
"gephy1_soft";
};
/* initial clocks and resets for third phy */
phy2 {
reg = <2>;
clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
clock-names = "gephy2_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY2_ARES>;
reset-names = "gephy2_sys",
"gephy2_soft";
};
/* initial clocks and resets for fourth phy */
phy3 {
reg = <3>;
clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
clock-names = "gephy3_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY3_ARES>;
reset-names = "gephy3_sys",
"gephy3_soft";
};
/* initial clocks and resets for pcs0. */
pcs0 {
reg = <4>;
clocks = <&qca8k_nsscc NSS_CC_SRDS0_SYS_CLK>;
clock-names = "srds0_sys";
resets = <&qca8k_nsscc NSS_CC_SRDS0_SYS_ARES>;
reset-names = "srds0_sys";
};
/* initial clocks and resets for pcs1. */
pcs1 {
reg = <5>;
clocks = <&qca8k_nsscc NSS_CC_SRDS1_SYS_CLK>;
clock-names = "srds1_sys";
resets = <&qca8k_nsscc NSS_CC_SRDS1_SYS_ARES>;
reset-names = "srds1_sys";
};
};
appreciated for the PHY package level DT model design.
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