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Message-ID: <20240110112059.2498-7-quic_luoj@quicinc.com>
Date: Wed, 10 Jan 2024 19:20:59 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: <andersson@...nel.org>, <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
<quic_kkumarcs@...cinc.com>, <quic_suruchia@...cinc.com>,
<quic_soni@...cinc.com>, <quic_pavir@...cinc.com>,
<quic_souravp@...cinc.com>, <quic_linchen@...cinc.com>,
<quic_leiwei@...cinc.com>
Subject: [PATCH 6/6] arm64: dts: qcom: ipq9574: Add RDP433 board device tree
From: Lei Wei <quic_leiwei@...cinc.com>
RDP433 board has four QCA8075 PHYs and two Aquantia 10G PHY onboard.
Signed-off-by: Lei Wei <quic_leiwei@...cinc.com>
Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 66 +++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 1bb8d96c9a82..298c0853b4d2 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -60,3 +60,69 @@ rclk-pins {
};
};
};
+
+&qcom_ppe {
+ qcom,port_phyinfo {
+ ppe_port0: port@0 {
+ port_id = <1>;
+ phy-mode = "qsgmii";
+ phy-handle = <&phy0>;
+ };
+ ppe_port1: port@1 {
+ port_id = <2>;
+ phy-mode = "qsgmii";
+ phy-handle = <&phy1>;
+ };
+ ppe_port2: port@2 {
+ port_id = <3>;
+ phy-mode = "qsgmii";
+ phy-handle = <&phy2>;
+ };
+ ppe_port3: port@3 {
+ port_id = <4>;
+ phy-mode = "qsgmii";
+ phy-handle = <&phy3>;
+ };
+ ppe_port4: port@4 {
+ port_id = <5>;
+ phy-mode = "usxgmii";
+ phy-handle = <&phy4>;
+ };
+ ppe_port5: port@5 {
+ port_id = <6>;
+ phy-mode = "usxgmii";
+ phy-handle = <&phy5>;
+ };
+ };
+};
+
+&mdio {
+ reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <16>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <17>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <18>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <19>;
+ };
+
+ phy4: ethernet-phy@4 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+
+ phy5: ethernet-phy@5 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+};
--
2.42.0
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