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Message-ID:
<AS8P193MB1285B34B71F3143FA9B0A053E4702@AS8P193MB1285.EURP193.PROD.OUTLOOK.COM>
Date: Fri, 19 Jan 2024 08:15:31 +0100
From: Bernd Edlinger <bernd.edlinger@...mail.de>
To: Jose Abreu <Jose.Abreu@...opsys.com>, Andrew Lunn <andrew@...n.ch>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"linux-stm32@...md-mailman.stormreply.com"
<linux-stm32@...md-mailman.stormreply.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Jiri Pirko <jiri@...dia.com>, Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [PATCH v2] net: stmmac: Wait a bit for the reset to take effect
On 1/17/24 17:55, Jose Abreu wrote:
> From: Bernd Edlinger <bernd.edlinger@...mail.de>
> Date: Wed, Jan 17, 2024 at 16:48:22
>
>> I don't know at all. And actually, I am more concerned that other registers
>> might be unreliable within the first microsecond after reset is de-asserted.
>
> Are you guaranteeing that the documented PoR time is achieved before reading registers?
>
Yes, that is the idea, why I added the udelay directly after releasing the reset,
thus simply delaying the execution of the stmmac_hw_init function, and not directly
where the synopsys_id register is accessed.
Thanks
Bernd.
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