netdev - [PATCH net-next v3 7/7] net: pcs: rzn1-miic: Init RX clock early if MAC requires it

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Message-Id: <20240212-rxc_bugfix-v3-7-e9f2eb6b3b05@bootlin.com>
Date: Mon, 12 Feb 2024 17:42:14 +0100
From: Romain Gantois <romain.gantois@...tlin.com>
To: Russell King <linux@...linux.org.uk>, Andrew Lunn <andrew@...n.ch>, 
 Heiner Kallweit <hkallweit1@...il.com>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Alexandre Torgue <alexandre.torgue@...s.st.com>, 
 Jose Abreu <joabreu@...opsys.com>, 
 Maxime Coquelin <mcoquelin.stm32@...il.com>, 
 Clément Léger <clement.leger@...tlin.com>
Cc: Maxime Chevallier <maxime.chevallier@...tlin.com>, 
 Miquel Raynal <miquel.raynal@...tlin.com>, 
 Thomas Petazzoni <thomas.petazzoni@...tlin.com>, netdev@...r.kernel.org, 
 linux-stm32@...md-mailman.stormreply.com, 
 linux-arm-kernel@...ts.infradead.org, linux-renesas-soc@...r.kernel.org, 
 Romain Gantois <romain.gantois@...tlin.com>
Subject: [PATCH net-next v3 7/7] net: pcs: rzn1-miic: Init RX clock early
 if MAC requires it

The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be
started before it initializes its own hardware, thus before it calls
phylink_start.

Check the rxc_always_on pcs flag and enable the clock signal during the
link validation phase.

Reported-by: Clément Léger <clement.leger@...tlin.com>
Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/
Signed-off-by: Romain Gantois <romain.gantois@...tlin.com>
---
 drivers/net/pcs/pcs-rzn1-miic.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index d93f84fbb1fd..b0d9736c678e 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -279,10 +279,37 @@ static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported,
 	return -EINVAL;
 }

+static int miic_pre_init(struct phylink_pcs *pcs)
+{
+	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
+	struct miic *miic = miic_port->miic;
+	u32 val;
+
+	/* Start RX clock if required */
+	if (pcs->rxc_always_on) {
+		/* In MII through mode, the clock signals will be driven by the
+		 * external PHY, which might not be initialized yet. Set RMII
+		 * as default mode to ensure that a reference clock signal is
+		 * generated.
+		 */
+		miic_port->interface = PHY_INTERFACE_MODE_RMII;
+
+		val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII);
+		miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port),
+			     MIIC_CONVCTRL_CONV_MODE,
+			     val);
+
+		miic_converter_enable(miic, miic_port->port, 1);
+	}
+
+	return 0;
+}
+
 static const struct phylink_pcs_ops miic_phylink_ops = {
 	.pcs_validate = miic_validate,
 	.pcs_config = miic_config,
 	.pcs_link_up = miic_link_up,
+	.pcs_pre_init = miic_pre_init,
 };

 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)

-- 
2.43.0