netdev - Re: [PATCH net-next v3 7/7] net: pcs: rzn1-miic: Init RX clock early if MAC requires it

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Message-ID: <20240212185332.2ebf2935@device-28.home>
Date: Mon, 12 Feb 2024 18:53:32 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: Romain Gantois <romain.gantois@...tlin.com>
Cc: Russell King <linux@...linux.org.uk>, Andrew Lunn <andrew@...n.ch>,
 Heiner Kallweit <hkallweit1@...il.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
 <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Alexandre Torgue
 <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, Maxime
 Coquelin <mcoquelin.stm32@...il.com>, Clément Léger
 <clement.leger@...tlin.com>, Miquel Raynal <miquel.raynal@...tlin.com>,
 Thomas Petazzoni <thomas.petazzoni@...tlin.com>, netdev@...r.kernel.org,
 linux-stm32@...md-mailman.stormreply.com,
 linux-arm-kernel@...ts.infradead.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH net-next v3 7/7] net: pcs: rzn1-miic: Init RX clock
 early if MAC requires it

Hi Romain,

On Mon, 12 Feb 2024 17:42:14 +0100
Romain Gantois <romain.gantois@...tlin.com> wrote:

> The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be
> started before it initializes its own hardware, thus before it calls
> phylink_start.
> 
> Check the rxc_always_on pcs flag and enable the clock signal during the
> link validation phase.

It looks like this commit log doesn't match the content of the commit.

> Reported-by: Clément Léger <clement.leger@...tlin.com>
> Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/
> Signed-off-by: Romain Gantois <romain.gantois@...tlin.com>
> ---
>  drivers/net/pcs/pcs-rzn1-miic.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
> index d93f84fbb1fd..b0d9736c678e 100644
> --- a/drivers/net/pcs/pcs-rzn1-miic.c
> +++ b/drivers/net/pcs/pcs-rzn1-miic.c
> @@ -279,10 +279,37 @@ static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported,
>  	return -EINVAL;
>  }
>  
> +static int miic_pre_init(struct phylink_pcs *pcs)
> +{
> +	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
> +	struct miic *miic = miic_port->miic;
> +	u32 val;
> +
> +	/* Start RX clock if required */
> +	if (pcs->rxc_always_on) {
> +		/* In MII through mode, the clock signals will be driven by the
> +		 * external PHY, which might not be initialized yet. Set RMII
> +		 * as default mode to ensure that a reference clock signal is
> +		 * generated.
> +		 */
> +		miic_port->interface = PHY_INTERFACE_MODE_RMII;

There's this check in miic_config :

	if (interface != miic_port->interface) {
		val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
		mask |= MIIC_CONVCTRL_CONV_SPEED;
		miic_port->interface = interface;
	}

As you set the interface to RMII and set the CONV_MODE below without
really looking at the speed, is there any risk of a mismatch between
the configured mode and the speed ?

Thanks,

Maxime