netdev - RE: [PATCH net-next v12 00/15] Introducing P4TC (series 1)

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Message-ID: <CO1PR11MB49931E501B20F32681F917CD935F2@CO1PR11MB4993.namprd11.prod.outlook.com>
Date: Thu, 29 Feb 2024 21:49:07 +0000
From: "Singhai, Anjali" <anjali.singhai@...el.com>
To: Paolo Abeni <pabeni@...hat.com>, "Hadi Salim, Jamal" <jhs@...atatu.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC: "Chatterjee, Deb" <deb.chatterjee@...el.com>, "Limaye, Namrata"
	<namrata.limaye@...el.com>, "tom@...anda.io" <tom@...anda.io>,
	"mleitner@...hat.com" <mleitner@...hat.com>, "Mahesh.Shirshyad@....com"
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	"bpf@...r.kernel.org" <bpf@...r.kernel.org>
Subject: RE: [PATCH net-next v12 00/15] Introducing P4TC (series 1)

From: Paolo Abeni <pabeni@...hat.com> 

> I think/fear that this series has a "quorum" problem: different voices raises opposition, and nobody (?) outside the authors
> supported the code and the feature. 

> Could be the missing of H/W offload support in the current form the root cause for such lack support? Or there are parties 
> interested that have been quite so far?

Hi,
   Intel/AMD definitely need the p4tc offload support and a kernel SW pipeline, as a lot of customers using programmable pipeline (smart switch and smart NIC) prefer kernel standard APIs and interfaces (netlink and tc ndo). Intel and other vendors have native P4 capable HW and are invested in P4 as a dataplane specification.

- Customers run P4 dataplane in multiple targets including SW pipeline as well as programmable Switches and DPUs.
- A standardized kernel APIs and implementation brings in portability across vendors and across targets (CPU/SW and DPUs).
- A P4 pipeline can be built using both SW and HW (DPU/switch) components and the P4 pipeline should seamlessly move between the two. 
- This patch series helps create a SW pipeline and standard API.

Thanks,
Anjali