Date: Thu, 29 Feb 2024 14:33:20 -0800
From: John Fastabend <john.fastabend@...il.com>
To: "Singhai, Anjali" <anjali.singhai@...el.com>, 
 Paolo Abeni <pabeni@...hat.com>, 
 "Hadi Salim, Jamal" <jhs@...atatu.com>, 
 "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Cc: "Chatterjee, Deb" <deb.chatterjee@...el.com>, 
 "Limaye, Namrata" <namrata.limaye@...el.com>, 
 "tom@...anda.io" <tom@...anda.io>, 
 "mleitner@...hat.com" <mleitner@...hat.com>, 
 "Mahesh.Shirshyad@....com" <Mahesh.Shirshyad@....com>, 
 "Vipin.Jain@....com" <Vipin.Jain@....com>, 
 "Osinski, Tomasz" <tomasz.osinski@...el.com>, 
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 "bpf@...r.kernel.org" <bpf@...r.kernel.org>
Subject: RE: [PATCH net-next v12 00/15] Introducing P4TC (series 1)

Singhai, Anjali wrote:
> From: Paolo Abeni <pabeni@...hat.com> 
> 
> > I think/fear that this series has a "quorum" problem: different voices raises opposition, and nobody (?) outside the authors
> > supported the code and the feature. 
> 
> > Could be the missing of H/W offload support in the current form the root cause for such lack support? Or there are parties 
> > interested that have been quite so far?
> 
> Hi,
>    Intel/AMD definitely need the p4tc offload support and a kernel SW pipeline, as a lot of customers using programmable pipeline (smart switch and smart NIC) prefer kernel standard APIs and interfaces (netlink and tc ndo). Intel and other vendors have native P4 capable HW and are invested in P4 as a dataplane specification.

Great what hardware/driver and how do we get that code here so we can see
it working? Is the hardware available e.g. can I get ahold of one?

What is programmable on your devices? Is this 'just' the parser graph or
are you slicing up tables and so on. Is it a FPGA, DPU architecture or a
TCAM architecture? How do you reprogram the device? I somehow doubt its
through a piecemeal ndo. But let me know if I'm wrong maybe my internal
architecture details are dated. Fully speculating the interface is a FW
big thunk to the device?

Without any details its difficult to get community feedback on how the
hw programmable interface should work. The only reason I've even
bothered with this thread is I want to see P4 working.

Who owns the AMD side or some other vendor so we can get something that
works across at least two vendors which is our usual bar for adding hw
offload things.

Note if you just want a kernel SW pipeline we already have that so
I'm not seeing that as paticularly motivating. Again my point of view.
P4 as a dataplane specification is great but I don't see the connection
to this patchset without real hardware in a driver.

> 
> - Customers run P4 dataplane in multiple targets including SW pipeline as well as programmable Switches and DPUs.
> - A standardized kernel APIs and implementation brings in portability across vendors and across targets (CPU/SW and DPUs).
> - A P4 pipeline can be built using both SW and HW (DPU/switch) components and the P4 pipeline should seamlessly move between the two. 
> - This patch series helps create a SW pipeline and standard API.
> 
> Thanks,
> Anjali
> 

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