[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <9d359843-e7a6-d2bc-cc7c-e7133ba3662e@intel.com>
Date: Mon, 6 May 2024 14:27:14 -0700
From: Tony Nguyen <anthony.l.nguyen@...el.com>
To: Ross Lagerwall <ross.lagerwall@...rix.com>, <netdev@...r.kernel.org>
CC: <intel-wired-lan@...ts.osuosl.org>, Jesse Brandeburg
<jesse.brandeburg@...el.com>, Javi Merino <javi.merino@...nel.org>
Subject: Re: [PATCH v2] ice: Fix enabling SR-IOV with Xen
On 4/29/2024 5:49 AM, Ross Lagerwall wrote:
> When the PCI functions are created, Xen is informed about them and
> caches the number of MSI-X entries each function has. However, the
> number of MSI-X entries is not set until after the hardware has been
> configured and the VFs have been started. This prevents
> PCI-passthrough from working because Xen rejects mapping MSI-X
> interrupts to domains because it thinks the MSI-X interrupts don't
> exist.
>
> Fix this by moving the call to pci_enable_sriov() later so that the
> number of MSI-X entries is set correctly in hardware by the time Xen
> reads it.
>
Sorry, I missed this on initial review, but bug fixes should have a
Fixes: tag
I assume you are targeting this for net, if so, can you mark it as
'PATCH iwl-net'.
> Signed-off-by: Ross Lagerwall <ross.lagerwall@...rix.com>
> Signed-off-by: Javi Merino <javi.merino@...nel.org>
Also, sender should be the last sign-off.
Thanks,
Tony
Powered by blists - more mailing lists