netdev - RE: [PATCH net] net: dsa: microchip: fix wrong register write when masking interrupt

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Message-ID: <BYAPR11MB3558611EBDCD3097B764D2C2ECF32@BYAPR11MB3558.namprd11.prod.outlook.com>
Date: Thu, 30 May 2024 23:17:42 +0000
From: <Tristram.Ha@...rochip.com>
To: <pabeni@...hat.com>
CC: <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
	<UNGLinuxDriver@...rochip.com>, <netdev@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <Arun.Ramadoss@...rochip.com>,
	<Woojung.Huh@...rochip.com>, <andrew@...n.ch>, <vivien.didelot@...il.com>,
	<f.fainelli@...il.com>, <olteanv@...il.com>
Subject: RE: [PATCH net] net: dsa: microchip: fix wrong register write when
 masking interrupt

> Subject: Re: [PATCH net] net: dsa: microchip: fix wrong register write when masking
> interrupt
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content
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> 
> On Tue, 2024-05-28 at 14:35 -0700, Tristram.Ha@...rochip.com wrote:
> > From: Tristram Ha <tristram.ha@...rochip.com>
> >
> > The initial code used 32-bit register.  After that it was changed to 0x1F
> > so it is no longer appropriate to use 32-bit write.
> 
> IMHO the above sentence is too much unclear. It sort of implies that
> the currently used register is 8 bit wide because such register address
> can be represented with 8 bit - which in turn sounds weird or
> irrelevant.
> 
> I guess some documentation describes register 0x1F, please rephrase the
> changelog accordingly.

I will clarify the comment.
Initially the REG_SW_PORT_INT_MASK__4 is defined as 0x001C in
ksz9477_reg.h and REG_PORT_INT_MASK is defined as 0x#01F.  Because the
global and port interrupt handling is about the same new
REG_SW_PORT_INT_MASK__1 is defined as 0x1F in ksz_common.h.  This works
as only the least significant bits have effect.  As a result the 32-bit
write needs to be changed to 8-bit.