netdev - Re: [PATCH net] net: dsa: microchip: fix wrong register write when masking interrupt

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6092d48946628c7e41fff25b161fdb71ce55d3d2.camel@redhat.com>
Date: Thu, 30 May 2024 10:56:22 +0200
From: Paolo Abeni <pabeni@...hat.com>
To: Tristram.Ha@...rochip.com, Arun Ramadoss <arun.ramadoss@...rochip.com>, 
 Woojung Huh <woojung.huh@...rochip.com>, Andrew Lunn <andrew@...n.ch>,
 Vivien Didelot <vivien.didelot@...il.com>, Florian Fainelli
 <f.fainelli@...il.com>,  Vladimir Oltean <olteanv@...il.com>
Cc: "David S. Miller" <davem@...emloft.net>, Eric Dumazet
 <edumazet@...gle.com>,  Jakub Kicinski <kuba@...nel.org>,
 UNGLinuxDriver@...rochip.com, netdev@...r.kernel.org, 
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH net] net: dsa: microchip: fix wrong register write when
 masking interrupt

On Tue, 2024-05-28 at 14:35 -0700, Tristram.Ha@...rochip.com wrote:
> From: Tristram Ha <tristram.ha@...rochip.com>
> 
> The initial code used 32-bit register.  After that it was changed to 0x1F
> so it is no longer appropriate to use 32-bit write.

IMHO the above sentence is too much unclear. It sort of implies that
the currently used register is 8 bit wide because such register address
can be represented with 8 bit - which in turn sounds weird or
irrelevant.

I guess some documentation describes register 0x1F, please rephrase the
changelog accordingly.

Thanks,

Paolo