netdev - Re: [PATCH net-next v13 02/15] net: stmmac: Add multi-channel support

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Date: Sat, 15 Jun 2024 17:18:14 +0800
From: Yanteng Si <siyanteng@...ngson.cn>
To: Serge Semin <fancer.lancer@...il.com>
Cc: andrew@...n.ch, hkallweit1@...il.com, peppe.cavallaro@...com,
 alexandre.torgue@...s.st.com, joabreu@...opsys.com, Jose.Abreu@...opsys.com,
 chenhuacai@...nel.org, linux@...linux.org.uk, guyinggang@...ngson.cn,
 netdev@...r.kernel.org, chris.chenfeiyang@...il.com, si.yanteng@...ux.dev
Subject: Re: [PATCH net-next v13 02/15] net: stmmac: Add multi-channel support


在 2024/6/14 21:31, Serge Semin 写道:
> Hi Yanteng
>
> On Wed, May 29, 2024 at 06:18:18PM +0800, Yanteng Si wrote:
>> DW GMAC v3.x multi-channels feature is implemented as multiple
>> sets of the same CSRs. Here is only preliminary support, it will
>> be useful for the driver further evolution and for the users
>> having multi-channel DWGMAC v3.x devices.
> Why haven't you picked up the commit log suggested on v12? It has more
> details about the feature and the change context. Please use it:
>
> "DW GMAC v3.73 can be equipped with the Audio Video (AV) feature which
> enables transmission of time-sensitive traffic over bridged local area
> networks (DWC Ethernet QoS Product). In that case there can be up to two
> additional DMA-channels available with no Tx COE support (unless there is
> vendor-specific IP-core alterations). Each channel is implemented as a
> separate Control and Status register (CSR) for managing the transmit and
> receive functions, descriptor handling, and interrupt handling.
>
> Add the multi-channels DW GMAC controllers support just by making sure the
> already implemented DMA-configs are performed on the per-channel basis.
>
> Note the only currently known instance of the multi-channel DW GMAC
> IP-core is the LS2K2000 GNET controller, which has been released with the
> vendor-specific feature extension of having eight DMA-channels. The device
> support will be added in one of the following up commits."
Oops! I will pick up in v14.
>
>> Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
>> Signed-off-by: Yinggang Gu <guyinggang@...ngson.cn>
>> Signed-off-by: Yanteng Si <siyanteng@...ngson.cn>
>> ---
>>   .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c |  2 +-
>>   .../ethernet/stmicro/stmmac/dwmac1000_dma.c   | 32 ++++++++++---------
>>
>>   	.axi = dwmac1000_dma_axi,
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
>> index 72672391675f..363a85469594 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
>> @@ -22,6 +22,23 @@
>>   #define DMA_INTR_ENA		0x0000101c	/* Interrupt Enable */
>>   #define DMA_MISSED_FRAME_CTR	0x00001020	/* Missed Frame Counter */
>>   
>> +/* Following DMA defines are channels oriented */
>> +#define DMA_CHAN_BASE_OFFSET			0x100
>> +
>> +static inline u32 dma_chan_base_addr(u32 base, u32 chan)
>> +{
>> +	return base + chan * DMA_CHAN_BASE_OFFSET;
>> +}
>> +
>> +#define DMA_CHAN_XMT_POLL_DEMAND(chan)	dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
>> +#define DMA_CHAN_INTR_ENA(chan)	dma_chan_base_addr(DMA_INTR_ENA, chan)
>> +#define DMA_CHAN_CONTROL(chan)		dma_chan_base_addr(DMA_CONTROL, chan)
>> +#define DMA_CHAN_STATUS(chan)		dma_chan_base_addr(DMA_STATUS, chan)
>> +#define DMA_CHAN_BUS_MODE(chan)	dma_chan_base_addr(DMA_BUS_MODE, chan)
>> +#define DMA_CHAN_RCV_BASE_ADDR(chan)	dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
>> +#define DMA_CHAN_TX_BASE_ADDR(chan)	dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
>> +#define DMA_CHAN_RX_WATCHDOG(chan)	dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
>> +
> Please re-define the macros in the address ascending order:
> DMA_CHAN_BUS_MODE()
> DMA_CHAN_XMT_POLL_DEMAND()
> DMA_CHAN_RCV_POLL_DEMAND()
> DMA_CHAN_RCV_BASE_ADDR()
> DMA_CHAN_TX_BASE_ADDR()
> DMA_CHAN_STATUS()
> DMA_CHAN_CONTROL()
> DMA_CHAN_INTR_ENA()
> DMA_CHAN_MISSED_FRAME_CTR()
> DMA_CHAN_RX_WATCHDOG()
>
> * Please don't forget DMA_CHAN_RCV_POLL_DEMAND() and
> DMA_CHAN_MISSED_FRAME_CTR() macros you've missed in your patch.
OK.
>>   /* SW Reset */
>>   #define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */
>>   
>> @@ -152,7 +169,7 @@
>>   #define NUM_DWMAC1000_DMA_REGS	23
>>   #define NUM_DWMAC4_DMA_REGS	27
>>   
>> -void dwmac_enable_dma_transmission(void __iomem *ioaddr);
>> +void dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan);
>>   void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
>>   			  u32 chan, bool rx, bool tx);
>>   void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
>> @@ -168,5 +185,4 @@ void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
>>   int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
>>   			struct stmmac_extra_stats *x, u32 chan, u32 dir);
>>   int dwmac_dma_reset(void __iomem *ioaddr);
>> -
> What has been wrong with this empty line so you decided to remove it?)

OK, will restore it.


Thanks,

Yanteng

>
> -Serge(y)
>