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Date: Mon, 17 Jun 2024 18:00:19 +0800
From: Yanteng Si <siyanteng@...ngson.cn>
To: Serge Semin <fancer.lancer@...il.com>
Cc: andrew@...n.ch, hkallweit1@...il.com, peppe.cavallaro@...com,
alexandre.torgue@...s.st.com, joabreu@...opsys.com, Jose.Abreu@...opsys.com,
chenhuacai@...nel.org, linux@...linux.org.uk, guyinggang@...ngson.cn,
netdev@...r.kernel.org, chris.chenfeiyang@...il.com, si.yanteng@...ux.dev
Subject: Re: [PATCH net-next v13 06/15] net: stmmac: dwmac-loongson: Detach
GMAC-specific platform data init
Hi Serge,
在 2024/6/15 00:19, Serge Semin 写道:
> On Wed, May 29, 2024 at 06:19:03PM +0800, Yanteng Si wrote:
>> Loongson delivers two types of the network devices: Loongson GMAC and
>> Loongson GNET in the framework of four CPU/Chipsets revisions:
>>
>> Chip Network PCI Dev ID Synopys Version DMA-channel
>> LS2K1000 CPU GMAC 0x7a03 v3.50a/v3.73a 1
>> LS7A1000 Chipset GMAC 0x7a03 v3.50a/v3.73a 1
>> LS2K2000 CPU GNET 0x7a13 v3.73a 8
>> LS7A2000 Chipset GNET 0x7a13 v3.73a 1
> You mentioned in the cover-letter
> https://lore.kernel.org/netdev/cover.1716973237.git.siyanteng@loongson.cn/
> that LS2K now have GMAC NICs too:
> " 1. The current LS2K2000 also have a GMAC(and two GNET) that supports 8
> channels, so we have to reconsider the initialization of
> tx/rx_queues_to_use into probe();"
>
> But I don't see much changes in the series which would indicate that
> new data. Please clarify what does it mean:
>
> Does it mean LS2K2000 has two types of the DW GMACs, right?
Yes!
>
> Are both of them based on the DW GMAC v3.73a IP-core with AV-feature
> enabled and 8 DMA-channels?
Yes!
>
> Seeing you called the new device as GMAC it doesn't have an
> integrated PHY as GNETs do, does it? If so, then neither
> STMMAC_FLAG_DISABLE_FORCE_1000 nor loongson_gnet_fix_speed() relevant
> for the new device, right?
YES!
>
> Why haven't you changed the sheet in the commit log? Shall the sheet
> be updated like this:
>
> Chip Network PCI Dev ID Synopys Version DMA-channel
> LS2K1000 CPU GMAC 0x7a03 v3.50a/v3.73a 1
> LS7A1000 Chipset GMAC 0x7a03 v3.50a/v3.73a 1
> +LS2K2000 CPU GMAC 0x7a13 v3.73a 8
> LS2K2000 CPU GNET 0x7a13 v3.73a 8
> LS7A2000 Chipset GNET 0x7a13 v3.73a 1
>
> ?
No! PCI Dev ID of GMAC is 0x7a03. So:
LS2K1000 CPU GMAC 0x7a03 v3.50a/v3.73a 1
LS7A1000 Chipset GMAC 0x7a03 v3.50a/v3.73a 1
+LS2K2000 CPU GMAC 0x7a03 v3.73a 8
LS2K2000 CPU GNET 0x7a13 v3.73a 8
LS7A2000 Chipset GNET 0x7a13 v3.73a 1
>
> I'll continue reviewing the series after the questions above are
> clarified.
OK, If anything else is unclear, please let me know.
Thanks,
Yanteng
>
> -Serge(y)
>
>> The driver currently supports the chips with the Loongson GMAC network
>> device. As a preparation before adding the Loongson GNET support
>> detach the Loongson GMAC-specific platform data initializations to the
>> loongson_gmac_data() method and preserve the common settings in the
>> loongson_default_data().
>>
>> While at it drop the return value statement from the
>> loongson_default_data() method as redundant.
>>
>> Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
>> Signed-off-by: Yinggang Gu <guyinggang@...ngson.cn>
>> Signed-off-by: Yanteng Si <siyanteng@...ngson.cn>
>> ---
>> .../ethernet/stmicro/stmmac/dwmac-loongson.c | 19 ++++++++++++-------
>> 1 file changed, 12 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
>> index 739b73f4fc35..ad3f44440963 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
>> @@ -11,7 +11,7 @@
>>
>> #define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03
>>
>> -static int loongson_default_data(struct plat_stmmacenet_data *plat)
>> +static void loongson_default_data(struct plat_stmmacenet_data *plat)
>> {
>> plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
>> plat->has_gmac = 1;
>> @@ -20,16 +20,14 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat)
>> /* Set default value for multicast hash bins */
>> plat->multicast_filter_bins = 256;
>>
>> + plat->mac_interface = PHY_INTERFACE_MODE_NA;
>> +
>> /* Set default value for unicast filter entries */
>> plat->unicast_filter_entries = 1;
>>
>> /* Set the maxmtu to a default of JUMBO_LEN */
>> plat->maxmtu = JUMBO_LEN;
>>
>> - /* Set default number of RX and TX queues to use */
>> - plat->tx_queues_to_use = 1;
>> - plat->rx_queues_to_use = 1;
>> -
>> /* Disable Priority config by default */
>> plat->tx_queues_cfg[0].use_prio = false;
>> plat->rx_queues_cfg[0].use_prio = false;
>> @@ -42,6 +40,11 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat)
>>
>> plat->dma_cfg->pbl = 32;
>> plat->dma_cfg->pblx8 = true;
>> +}
>> +
>> +static int loongson_gmac_data(struct plat_stmmacenet_data *plat)
>> +{
>> + loongson_default_data(plat);
>>
>> return 0;
>> }
>> @@ -111,11 +114,10 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
>> }
>>
>> plat->phy_interface = phy_mode;
>> - plat->mac_interface = PHY_INTERFACE_MODE_GMII;
>>
>> pci_set_master(pdev);
>>
>> - loongson_default_data(plat);
>> + loongson_gmac_data(plat);
>> pci_enable_msi(pdev);
>> memset(&res, 0, sizeof(res));
>> res.addr = pcim_iomap_table(pdev)[0];
>> @@ -140,6 +142,9 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
>> goto err_disable_msi;
>> }
>>
>> + plat->tx_queues_to_use = 1;
>> + plat->rx_queues_to_use = 1;
>> +
>> ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
>> if (ret)
>> goto err_disable_msi;
>> --
>> 2.31.4
>>
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