netdev - [PATCH V4 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node

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Date: Tue, 25 Jun 2024 12:35:35 +0530
From: Devi Priya <quic_devipriy@...cinc.com>
To: andersson@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
        robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
        konrad.dybcio@...aro.org, catalin.marinas@....com, will@...nel.org,
        p.zabel@...gutronix.de, richardcochran@...il.com,
        geert+renesas@...der.be, dmitry.baryshkov@...aro.org,
        neil.armstrong@...aro.org, arnd@...db.de, m.szyprowski@...sung.com,
        nfraprado@...labora.com, u-kumar1@...com,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, netdev@...r.kernel.org
Cc: quic_devipriy@...cinc.com
Subject: [PATCH V4 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node

Add a node for the nss clock controller found on ipq9574 based devices.

Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
---
 Changes in V4:
	- Added GCC_NSSCC_CLK to the nsscc node
	- Added interconnects and interconnect-names for enabling the NoC clocks.

 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 44 +++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 48dfafea46a7..c4855b959159 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -11,6 +11,8 @@
 #include <dt-bindings/interconnect/qcom,ipq9574.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -19,6 +21,24 @@ / {
 	#size-cells = <2>;
 
 	clocks {
+		bias_pll_cc_clk: bias-pll-cc-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1200000000>;
+			#clock-cells = <0>;
+		};
+
+		bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <461500000>;
+			#clock-cells = <0>;
+		};
+
+		bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <353000000>;
+			#clock-cells = <0>;
+		};
+
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -756,6 +776,30 @@ frame@...8000 {
 				status = "disabled";
 			};
 		};
+
+		nsscc: clock-controller@...00000 {
+			compatible = "qcom,ipq9574-nsscc";
+			reg = <0x39b00000 0x80000>;
+			clocks = <&xo_board_clk>,
+				 <&bias_pll_cc_clk>,
+				 <&bias_pll_nss_noc_clk>,
+				 <&bias_pll_ubi_nc_clk>,
+				 <&gcc GPLL0_OUT_AUX>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <&gcc GCC_NSSCC_CLK>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			interconnects = <&gcc MASTER_NSSNOC_NSSCC &gcc MASTER_NSSNOC_NSSCC>,
+					<&gcc MASTER_NSSNOC_SNOC_0 &gcc MASTER_NSSNOC_SNOC_0>,
+					<&gcc MASTER_NSSNOC_SNOC_1 &gcc MASTER_NSSNOC_SNOC_1>;
+			interconnect-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1";
+		};
 	};
 
 	thermal-zones {
-- 
2.34.1