netdev - [PATCH V4 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out

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Message-Id: <20240625070536.3043630-4-quic_devipriy@quicinc.com>
Date: Tue, 25 Jun 2024 12:35:32 +0530
From: Devi Priya <quic_devipriy@...cinc.com>
To: andersson@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
        robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
        konrad.dybcio@...aro.org, catalin.marinas@....com, will@...nel.org,
        p.zabel@...gutronix.de, richardcochran@...il.com,
        geert+renesas@...der.be, dmitry.baryshkov@...aro.org,
        neil.armstrong@...aro.org, arnd@...db.de, m.szyprowski@...sung.com,
        nfraprado@...labora.com, u-kumar1@...com,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, netdev@...r.kernel.org
Cc: quic_devipriy@...cinc.com
Subject: [PATCH V4 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock

Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (nss) clocks.

Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
---
 Changes in V4:
	- Reverted the changes to drop few nss clocks from the clock table and
	  enabling them from the probe as they are being enabled by the consumer
	  via interconnect.

 drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 80fc94d705a0..5dac3facc3a5 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 	},
 };
 
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+	.offset = 0x20000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "gpll0_out_aux",
+		.parent_hws = (const struct clk_hw *[]) {
+			&gpll0_main.clkr.hw
+		},
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+	},
+};
+
 static struct clk_alpha_pll gpll4_main = {
 	.offset = 0x22000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
 	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
 	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
 	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
+	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
-- 
2.34.1