netdev - Re: [PATCH v2 iwl-next 1/4] ice: Implement PTP support for E830 devices

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Message-ID: <2b992595-5b6b-e741-0dd0-f1e45538e68b@intel.com>
Date: Tue, 23 Jul 2024 15:05:06 -0700
From: Tony Nguyen <anthony.l.nguyen@...el.com>
To: Karol Kolacinski <karol.kolacinski@...el.com>,
	<intel-wired-lan@...ts.osuosl.org>
CC: <netdev@...r.kernel.org>, <przemyslaw.kitszel@...el.com>, Michal Michalik
	<michal.michalik@...el.com>, Milena Olech <milena.olech@...el.com>, "Paul
 Greenwalt" <paul.greenwalt@...el.com>
Subject: Re: [PATCH v2 iwl-next 1/4] ice: Implement PTP support for E830
 devices



On 7/11/2024 2:24 AM, Karol Kolacinski wrote:
> From: Michal Michalik <michal.michalik@...el.com>

...


> --- a/drivers/net/ethernet/intel/ice/ice_common.c
> +++ b/drivers/net/ethernet/intel/ice/ice_common.c
> @@ -307,6 +307,17 @@ bool ice_is_e825c(struct ice_hw *hw)
>   	}
>   }
>   
> +/**
> + * ice_is_e830
> + * @hw: pointer to the hardware structure
> + *
> + * returns true if the device is E830 based, false if not.

kdoc is looking for Return: or Returns:, please fix

> + */
> +bool ice_is_e830(const struct ice_hw *hw)
> +{
> +	return hw->mac_type == ICE_MAC_E830;
> +}
> +

...

> +/* E830 functions
> + *
> + * The following functions operate on the E830 series devices.
> + *
> + */
> +
> +/**
> + * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization
> + * @hw: pointer to HW struct
> + *
> + * Perform E830-specific PTP hardware clock initialization steps.
> + */

It's also flagging all the new functions for missing the return.

Thanks,
Tony

> +static int ice_ptp_init_phc_e830(struct ice_hw *hw)
> +{
> +	ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY);
> +	return 0;
> +}
> +
> +/**
> + * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change
> + * @hw: pointer to HW struct
> + * @incval: The new 40bit increment value to prepare
> + *
> + * Prepare the PHY port for a new increment value by programming the PHC
> + * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is
> + * completed by FW automatically.
> + */
> +static int ice_ptp_write_direct_incval_e830(struct ice_hw *hw, u64 incval)
> +{
> +	u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
> +
> +	wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval));
> +	wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval));
> +
> +	return 0;
> +}
> +
> +/**
> + * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time
> + * @hw: Board private structure
> + * @time: Time to initialize the PHY port clock to
> + *
> + * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
> + * initial clock time. The time will not actually be programmed until the
> + * driver issues an ICE_PTP_INIT_TIME command.
> + *
> + * The time value is the upper 32 bits of the PHY timer, usually in units of
> + * nominal nanoseconds.
> + */
> +static int ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time)
> +{
> +	u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
> +
> +	wr32(hw, GLTSYN_TIME_0(tmr_idx), 0);
> +	wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time));
> +	wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time));
> +
> +	return 0;
> +}
> +
> +/**
> + * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
> + * @hw: pointer to HW struct
> + * @cmd: Command to be sent to the port
> + *
> + * Prepare the external PHYs connected to this device for a timer sync
> + * command.
> + */
> +static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
> +{
> +	u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
> +
> +	return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val);
> +}
> +
> +/**
> + * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY
> + * @hw: pointer to the HW struct
> + * @lport: the lport to read from
> + * @idx: the timestamp index to read
> + * @tstamp: on return, the 40bit timestamp value
> + *
> + * Read a 40bit timestamp value out of the timestamp block of the external PHY
> + * on the E830 device.
> + */
> +static int
> +ice_read_phy_tstamp_e830(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
> +{
> +	u32 hi, lo;
> +
> +	hi = rd32(hw, E830_HIGH_TX_MEMORY_BANK(idx, lport));
> +	lo = rd32(hw, E830_LOW_TX_MEMORY_BANK(idx, lport));
> +
> +	/* For E830 devices, the timestamp is reported with the lower 32 bits
> +	 * in the low register, and the upper 8 bits in the high register.
> +	 */
> +	*tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) |
> +		  FIELD_PREP(PHY_EXT_40B_LOW_M, lo);
> +
> +	return 0;
> +}
> +
> +/**
> + * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register
> + * @hw: pointer to the HW struct
> + * @port: the PHY port to read
> + * @tstamp_ready: contents of the Tx memory status register
> + *
> + */
> +static int
> +ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
> +{
> +	*tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H);
> +	*tstamp_ready <<= 32;
> +	*tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L);
> +
> +	return 0;
> +}