| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <E1sZpol-000eHs-Cn@rmk-PC.armlinux.org.uk>
Date: Fri, 02 Aug 2024 11:47:27 +0100
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Serge Semin <fancer.lancer@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Alexei Starovoitov <ast@...nel.org>,
Andrew Halaney <ahalaney@...hat.com>,
bpf@...r.kernel.org,
Daniel Borkmann <daniel@...earbox.net>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Jesper Dangaard Brouer <hawk@...nel.org>,
John Fastabend <john.fastabend@...il.com>,
Jose Abreu <joabreu@...opsys.com>,
linux-arm-kernel@...ts.infradead.org,
linux-arm-msm@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>,
Vinod Koul <vkoul@...nel.org>
Subject: [PATCH net-next 12/14] net: stmmac: rename PCS registers
Rename the PCS registers from GMAC_xxx to STMMAC_PCS_xxx to make it
clear that they are for the PCS. Avoid using PCS_ as this is too
generic and may (eventually) clash with definitions elsewhere in the
kernel.
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 16 +++---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.h | 52 +++++++++----------
2 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index e435facc9849..7960bfd83b74 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -8,26 +8,26 @@ static void __dwmac_ctrl_ane(struct stmmac_pcs *spcs, bool ane, bool srgmi_ral,
{
u32 val;
- val = readl(spcs->pcs_base + GMAC_AN_CTRL(0));
+ val = readl(spcs->pcs_base + STMMAC_PCS_AN_CTRL);
/* Enable and restart the Auto-Negotiation */
if (ane)
- val |= GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_RAN;
+ val |= STMMAC_PCS_AN_CTRL_ANE | STMMAC_PCS_AN_CTRL_RAN;
else
- val &= ~GMAC_AN_CTRL_ANE;
+ val &= ~STMMAC_PCS_AN_CTRL_ANE;
/* In case of MAC-2-MAC connection, block is configured to operate
* according to MAC conf register.
*/
if (srgmi_ral)
- val |= GMAC_AN_CTRL_SGMRAL;
+ val |= STMMAC_PCS_AN_CTRL_SGMRAL;
if (loopback)
- val |= GMAC_AN_CTRL_ELE;
+ val |= STMMAC_PCS_AN_CTRL_ELE;
else
- val &= ~GMAC_AN_CTRL_ELE;
+ val &= ~STMMAC_PCS_AN_CTRL_ELE;
- writel(val, spcs->pcs_base + GMAC_AN_CTRL(0));
+ writel(val, spcs->pcs_base + STMMAC_PCS_AN_CTRL);
}
/**
@@ -53,7 +53,7 @@ int dwmac_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
- /* The RGMII interface does not have the GMAC_AN_CTRL register */
+ /* The RGMII interface does not have the STMMAC_PCS_AN_CTRL register */
if (phy_interface_mode_is_rgmii(spcs->priv->plat->mac_interface))
return 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index c73a08dab7b2..1827c7e64dba 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -14,37 +14,37 @@
#include "common.h"
/* PCS registers (AN/TBI/SGMII/RGMII) offsets */
-#define GMAC_AN_CTRL(x) (x) /* AN control */
-#define GMAC_AN_STATUS(x) (x + 0x4) /* AN status */
+#define STMMAC_PCS_AN_CTRL 0x00 /* AN control */
+#define STMMAC_PCS_AN_STATUS 0x04 /* AN status */
/* ADV, LPA and EXP are only available for the TBI and RTBI interfaces */
-#define GMAC_ANE_ADV(x) (x + 0x8) /* ANE Advertisement */
-#define GMAC_ANE_LPA(x) (x + 0xc) /* ANE link partener ability */
-#define GMAC_ANE_EXP(x) (x + 0x10) /* ANE expansion */
-#define GMAC_TBI(x) (x + 0x14) /* TBI extend status */
+#define STMMAC_PCS_ANE_ADV 0x08 /* ANE Advertisement */
+#define STMMAC_PCS_ANE_LPA 0x0c /* ANE link partener ability */
+#define STMMAC_PCS_ANE_EXP 0x10 /* ANE expansion */
+#define STMMAC_PCS_TBI 0x14 /* TBI extend status */
/* AN Configuration defines */
-#define GMAC_AN_CTRL_RAN BIT(9) /* Restart Auto-Negotiation */
-#define GMAC_AN_CTRL_ANE BIT(12) /* Auto-Negotiation Enable */
-#define GMAC_AN_CTRL_ELE BIT(14) /* External Loopback Enable */
-#define GMAC_AN_CTRL_ECD BIT(16) /* Enable Comma Detect */
-#define GMAC_AN_CTRL_LR BIT(17) /* Lock to Reference */
-#define GMAC_AN_CTRL_SGMRAL BIT(18) /* SGMII RAL Control */
+#define STMMAC_PCS_AN_CTRL_RAN BIT(9) /* Restart Auto-Negotiation */
+#define STMMAC_PCS_AN_CTRL_ANE BIT(12) /* Auto-Negotiation Enable */
+#define STMMAC_PCS_AN_CTRL_ELE BIT(14) /* External Loopback Enable */
+#define STMMAC_PCS_AN_CTRL_ECD BIT(16) /* Enable Comma Detect */
+#define STMMAC_PCS_AN_CTRL_LR BIT(17) /* Lock to Reference */
+#define STMMAC_PCS_AN_CTRL_SGMRAL BIT(18) /* SGMII RAL Control */
/* AN Status defines */
-#define GMAC_AN_STATUS_LS BIT(2) /* Link Status 0:down 1:up */
-#define GMAC_AN_STATUS_ANA BIT(3) /* Auto-Negotiation Ability */
-#define GMAC_AN_STATUS_ANC BIT(5) /* Auto-Negotiation Complete */
-#define GMAC_AN_STATUS_ES BIT(8) /* Extended Status */
+#define STMMAC_PCS_AN_STATUS_LS BIT(2) /* Link Status 0:down 1:up */
+#define STMMAC_PCS_AN_STATUS_ANA BIT(3) /* Auto-Negotiation Ability */
+#define STMMAC_PCS_AN_STATUS_ANC BIT(5) /* Auto-Negotiation Complete */
+#define STMMAC_PCS_AN_STATUS_ES BIT(8) /* Extended Status */
/* ADV and LPA defines */
-#define GMAC_ANE_FD BIT(5)
-#define GMAC_ANE_HD BIT(6)
-#define GMAC_ANE_PSE GENMASK(8, 7)
-#define GMAC_ANE_PSE_SHIFT 7
-#define GMAC_ANE_RFE GENMASK(13, 12)
-#define GMAC_ANE_RFE_SHIFT 12
-#define GMAC_ANE_ACK BIT(14)
+#define STMMAC_PCS_ANE_FD BIT(5)
+#define STMMAC_PCS_ANE_HD BIT(6)
+#define STMMAC_PCS_ANE_PSE GENMASK(8, 7)
+#define STMMAC_PCS_ANE_PSE_SHIFT 7
+#define STMMAC_PCS_ANE_RFE GENMASK(13, 12)
+#define STMMAC_PCS_ANE_RFE_SHIFT 12
+#define STMMAC_PCS_ANE_ACK BIT(14)
/* MAC specific status - for RGMII and SGMII. These appear as
* GMAC_RGSMIIIS[15:0] and GMAC_PHYIF_CONTROL_STATUS[31:16]
@@ -72,17 +72,17 @@ static inline void dwmac_pcs_isr(struct stmmac_pcs *spcs,
unsigned int intr_status,
struct stmmac_extra_stats *x)
{
- u32 val = readl(spcs->pcs_base + GMAC_AN_STATUS(0));
+ u32 val = readl(spcs->pcs_base + STMMAC_PCS_AN_STATUS);
if (intr_status & PCS_ANE_IRQ) {
x->irq_pcs_ane_n++;
- if (val & GMAC_AN_STATUS_ANC)
+ if (val & STMMAC_PCS_AN_STATUS_ANC)
pr_info("stmmac_pcs: ANE process completed\n");
}
if (intr_status & PCS_LINK_IRQ) {
x->irq_pcs_link_n++;
- if (val & GMAC_AN_STATUS_LS)
+ if (val & STMMAC_PCS_AN_STATUS_LS)
pr_info("stmmac_pcs: Link Up\n");
else
pr_info("stmmac_pcs: Link Down\n");
--
2.30.2
Powered by blists - more mailing lists