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Message-ID: <209287d5-4dac-48e1-ad15-6fd207bdbc9e@quicinc.com>
Date: Tue, 10 Sep 2024 16:25:12 -0700
From: "Abhishek Chauhan (ABC)" <quic_abchauha@...cinc.com>
To: Andrew Halaney <ahalaney@...hat.com>
CC: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu
<joabreu@...opsys.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet
<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni
<pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>, <netdev@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <kernel@...cinc.com>
Subject: Re: [PATCH net-next v1] net: stmmac: Programming sequence for VLAN
packets with split header
On 9/6/2024 2:49 PM, Andrew Halaney wrote:
> On Wed, Sep 04, 2024 at 04:54:56PM GMT, Abhishek Chauhan wrote:
>> Currently reset state configuration of split header works fine for
>> non-tagged packets and we see no corruption in payload of any size
>>
>> We need additional programming sequence with reset configuration to
>> handle VLAN tagged packets to avoid corruption in payload for packets
>> of size greater than 256 bytes.
>>
>> Without this change ping application complains about corruption
>> in payload when the size of the VLAN packet exceeds 256 bytes.
>>
>> With this change tagged and non-tagged packets of any size works fine
>> and there is no corruption seen.
>
> My real limited understanding from offline convos with you is that:
>
> 1. This changes splitting from L3 mode to L2? This maybe a "dumb"
> wording, but the L2 comment you have below reinforces that.
> Sorry, I don't have a very good mental model of what SPH is doing
i will explain more in detail as part of my next patch.From what i understood from the databook is
MAC has intelligence to know if the packet has VLAN header vs Normal Ethernet frame.
Based on that the programming sequence is followed to make sure split happens correctly
for Vlan packet vs non-Vlan packet.
> 2. This addresses the root issue of a few of the commits in
> stmmac that disable split header? Patches like
> 47f753c1108e net: stmmac: disable Split Header (SPH) for Intel platforms
> 029c1c2059e9 net: stmmac: dwc-qos: Disable split header for Tegra194
> ?
>
> If 1 is true I suggest making trying to paint a higher level intro picture to
> reviewers of what the prior programming enabled vs what you've enabled.
> It would help me at least!
>
> If 2 is true I suggest calling that out and Cc'ing the authors of those
> patches in hopes that they may try and re-enable SPH. If its not true
> (maybe there's an errata?) I'd be interested in knowing if there's a more
> generic way to disable SPH for those platforms instead of playing
> whack-a-mole per platform. That's a bit outside of the series here though,
> but I imagine you may have enough information to help answer those sort of
> questions and clean up the house here :)
I will add the folks in cc. If they are interested to test this out its even
better.
>
> Thanks,
> Andrew
>
>
>>
>> Signed-off-by: Abhishek Chauhan <quic_abchauha@...cinc.com>
>> ---
>> Changes since v0
>> - The reason for posting it on net-next is to enable this new feature.
>>
>> drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 9 +++++++++
>> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 11 +++++++++++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
>> index 93a78fd0737b..4e340937dc78 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
>> @@ -44,6 +44,7 @@
>> #define GMAC_MDIO_DATA 0x00000204
>> #define GMAC_GPIO_STATUS 0x0000020C
>> #define GMAC_ARP_ADDR 0x00000210
>> +#define GMAC_EXT_CFG1 0x00000238
>> #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
>> #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
>> #define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30)
>> @@ -235,6 +236,14 @@ enum power_event {
>> #define GMAC_CONFIG_HDSMS_SHIFT 20
>> #define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
>>
>> +/* MAC extended config1 */
>> +#define GMAC_CONFIG1_SAVE_EN BIT(24)
>> +#define GMAC_CONFIG1_SPLM GENMASK(9, 8)
>> +#define GMAC_CONFIG1_SPLM_L2OFST_EN BIT(0)
>> +#define GMAC_CONFIG1_SPLM_SHIFT 8
>> +#define GMAC_CONFIG1_SAVO GENMASK(22, 16)
>> +#define GMAC_CONFIG1_SAVO_SHIFT 16
>> +
>> /* MAC HW features0 bitmap */
>> #define GMAC_HW_FEAT_SAVLANINS BIT(27)
>> #define GMAC_HW_FEAT_ADDMAC BIT(18)
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
>> index e0165358c4ac..dbd1be4e4a92 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
>> @@ -526,6 +526,17 @@ static void dwmac4_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
>> value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
>> writel(value, ioaddr + GMAC_EXT_CONFIG);
>>
>> + /* Additional configuration to handle VLAN tagged packets */
>> + value = readl(ioaddr + GMAC_EXT_CFG1);
>> + value &= ~GMAC_CONFIG1_SPLM;
>> + /* Enable Split mode for header and payload at L2 */
>> + value |= GMAC_CONFIG1_SPLM_L2OFST_EN << GMAC_CONFIG1_SPLM_SHIFT;
>> + value &= ~GMAC_CONFIG1_SAVO;
>> + /* Enables the MAC to distinguish between tagged vs untagged pkts */
>> + value |= 4 << GMAC_CONFIG1_SAVO_SHIFT;
>> + value |= GMAC_CONFIG1_SAVE_EN;
>> + writel(value, ioaddr + GMAC_EXT_CFG1);
>> +
>> value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
>> if (en)
>> value |= DMA_CONTROL_SPH;
>> --
>> 2.25.1
>>
>
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