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Message-ID: <trinity-0e61ef5a-b461-485b-a7ea-787ffe9b1689-1726083054223@3c-app-gmx-bs04>
Date: Wed, 11 Sep 2024 21:30:54 +0200
From: Hans-Frieder Vogt <hfdevel@....net>
To: netdev@...r.kernel.org
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
 Russell King <linux@...linux.org.uk>, FUJITA Tomonori
 <fujita.tomonori@...il.com>, "David S. Miller" <davem@...emloft.net>, Eric
 Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo
 Abeni <pabeni@...hat.com>
Subject: [PATCH net-next 4/5] net: tn40xx: enable driver to support TN4010
 cards with AQR105 PHY

Prepare the tn40xx driver to load for Tehuti TN9510 cards
and set bit 3 in the TN40_REG_MDIO_CMD_STAT register, because otherwise the
AQR105 PHY will not be found. The function of bit 3 is unclear, but may have
something to do with the length of the preamble in MDIO communication.

Signed-off-by: Hans-Frieder Vogt <hfdevel@....net>
---
 drivers/net/ethernet/tehuti/tn40.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/tehuti/tn40.c b/drivers/net/ethernet/tehuti/tn40.c
index 259bdac24cf2..4e6f2f781ffc 100644
--- a/drivers/net/ethernet/tehuti/tn40.c
+++ b/drivers/net/ethernet/tehuti/tn40.c
@@ -1760,6 +1760,9 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		goto err_unset_drvdata;
 	}

+	/* essential for identification of some PHYs is bit 3 set */
+	ret = tn40_read_reg(priv, TN40_REG_MDIO_CMD_STAT);
+	tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, ret | 0x8);
 	ret = tn40_mdiobus_init(priv);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to initialize mdio bus.\n");
@@ -1832,6 +1835,7 @@ static const struct pci_device_id tn40_id_table[] = {
 			 PCI_VENDOR_ID_ASUSTEK, 0x8709) },
 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022,
 			 PCI_VENDOR_ID_EDIMAX, 0x8103) },
+	{ PCI_VDEVICE(TEHUTI, 0x4025), 0 },
 	{ }
 };

--
2.45.2


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