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Message-ID:
<ZQ2PR01MB13071A093EB33F48340F753EE66F2@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn>
Date: Mon, 23 Sep 2024 07:53:24 +0000
From: Hal Feng <hal.feng@...rfivetech.com>
To: Andrew Lunn <andrew@...n.ch>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Marc Kleine-Budde <mkl@...gutronix.de>,
Vincent Mailhol <mailhol.vincent@...adoo.fr>, "David S . Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Philipp Zabel
<p.zabel@...gutronix.de>, Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley
<paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu>, Emil Renner
Berthing <emil.renner.berthing@...onical.com>, William Qiu
<william.qiu@...rfivetech.com>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-can@...r.kernel.org"
<linux-can@...r.kernel.org>, "netdev@...r.kernel.org"
<netdev@...r.kernel.org>, "linux-riscv@...ts.infradead.org"
<linux-riscv@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 3/4] can: Add driver for CAST CAN Bus Controller
> On 23.09.24 00:34, Andrew Lunn wrote:
> > +static inline u32 ccan_read_reg(const struct ccan_priv *priv, u8 reg)
> > +{
> > + return ioread32(priv->reg_base + reg); }
> > +
> > +static inline void ccan_write_reg(const struct ccan_priv *priv, u8
> > +reg, u32 value) {
> > + iowrite32(value, priv->reg_base + reg); }
>
> No inline functions in .c files please. Let the compiler decide.
OK. Drop them.
>
> > +static inline u8 ccan_read_reg_8bit(const struct ccan_priv *priv,
> > + enum ccan_reg reg)
> > +{
> > + u8 reg_down;
> > + union val {
> > + u8 val_8[4];
> > + u32 val_32;
> > + } val;
> > +
> > + reg_down = ALIGN_DOWN(reg, 4);
> > + val.val_32 = ccan_read_reg(priv, reg_down);
> > + return val.val_8[reg - reg_down];
>
> There is an ioread8(). Is it invalid to do a byte read for this hardware? If so, it is
> probably worth a comment.
The hardware has been initially developed as peripheral component for 8 bit systems
and therefore control and status registers defined as 8 bit groups. Nevertheless
the hardware is designed as a 32 bit component finally. It prefers 32-bit read/write
interfaces. I will add a comment later.
>
> > +static int ccan_bittime_configuration(struct net_device *ndev) {
> > + struct ccan_priv *priv = netdev_priv(ndev);
> > + struct can_bittiming *bt = &priv->can.bittiming;
> > + struct can_bittiming *dbt = &priv->can.data_bittiming;
> > + u32 bittiming, data_bittiming;
> > + u8 reset_test;
> > +
> > + reset_test = ccan_read_reg_8bit(priv, CCAN_CFG_STAT);
> > +
> > + if (!(reset_test & CCAN_RST_MASK)) {
> > + netdev_alert(ndev, "Not in reset mode, cannot set bit
> timing\n");
> > + return -EPERM;
> > + }
>
>
> You don't see nedev_alert() used very often. If this is fatal then netdev_err().
>
> Also, EPERM? man 3 errno say:
>
> EPERM Operation not permitted (POSIX.1-2001).
>
> Why is this a permission issue?
Will use netdev_err() and return -EWOULDBLOCK instead.
>
> > +static void ccan_tx_interrupt(struct net_device *ndev, u8 isr) {
> > + struct ccan_priv *priv = netdev_priv(ndev);
> > +
> > + /* wait till transmission of the PTB or STB finished */
> > + while (isr & (CCAN_TPIF_MASK | CCAN_TSIF_MASK)) {
> > + if (isr & CCAN_TPIF_MASK)
> > + ccan_reg_set_bits(priv, CCAN_RTIF,
> CCAN_TPIF_MASK);
> > +
> > + if (isr & CCAN_TSIF_MASK)
> > + ccan_reg_set_bits(priv, CCAN_RTIF,
> CCAN_TSIF_MASK);
> > +
> > + isr = ccan_read_reg_8bit(priv, CCAN_RTIF);
> > + }
>
> Potentially endless loops like this are a bad idea. If the firmware crashes, you
> are never getting out of here. Please use one of the macros from iopoll.h
Agree with you. Will modify accordingly.
>
> > +static irqreturn_t ccan_interrupt(int irq, void *dev_id) {
> > + struct net_device *ndev = (struct net_device *)dev_id;
>
> dev_id is a void *, so you don't need the cast.
OK, drop it.
Thanks for you review.
Best regards,
Hal
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