netdev - Re: [PATCH] net: stmmac: dwmac-tegra: Fix link bring-up sequence

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Message-ID: <fb04a8c0-371d-43a8-b345-44a226d57eb4@nvidia.com>
Date: Tue, 24 Sep 2024 11:08:32 +0100
From: Jon Hunter <jonathanh@...dia.com>
To: Paritosh Dixit <paritoshd@...dia.com>,
 Alexandre Torgue <alexandre.torgue@...s.st.com>,
 Jose Abreu <joabreu@...opsys.com>, "David S . Miller" <davem@...emloft.net>,
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>, Maxime Coquelin
 <mcoquelin.stm32@...il.com>, Thierry Reding <thierry.reding@...il.com>
Cc: Bhadram Varka <vbhadram@...dia.com>,
 Revanth Kumar Uppala <ruppala@...dia.com>, netdev@...r.kernel.org,
 linux-tegra@...r.kernel.org
Subject: Re: [PATCH] net: stmmac: dwmac-tegra: Fix link bring-up sequence


On 23/09/2024 14:44, Paritosh Dixit wrote:
> The Tegra MGBE driver sometimes fails to initialize, reporting the
> following error, and as a result, it is unable to acquire an IP
> address with DHCP:
> 
>   tegra-mgbe 6800000.ethernet: timeout waiting for link to become ready
> 
> As per the recommendation from the Tegra hardware design team, fix this
> issue by:
> - clearing the PHY_RDY bit before setting the CDR_RESET bit and then
> setting PHY_RDY bit before clearing CDR_RESET bit. This ensures valid
> data is present at UPHY RX inputs before starting the CDR lock.
> - adding the required delays when bringing up the UPHY lane. Note we
> need to use delays here because there is no alternative, such as
> polling, for these cases.
> 
> Without this change we would see link failures on boot sometimes as
> often as 1 in 5 boots. With this fix we have not observed any failures
> in over 1000 boots.
> 
> Fixes: d8ca113724e7 ("net: stmmac: tegra: Add MGBE support")
> Signed-off-by: Paritosh Dixit <paritoshd@...dia.com>
> ---
>   drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c | 14 ++++++++++++--
>   1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
> index 362f85136c3e..c81ae5f8fef4 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
> @@ -127,10 +127,12 @@ static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_
>   	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   
> +	ndelay(50);  // 50ns min delay needed as per HW design
>   	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   
> +	ndelay(500);  // 500ns min delay needed as per HW design
>   	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> @@ -143,22 +145,30 @@ static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_
>   		return err;
>   	}
>   
> +	ndelay(50);  // 50ns min delay needed as per HW design
>   	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   
>   	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> -	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
> +	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   
> +	ndelay(50);  // 50ns min delay needed as per HW design
>   	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> -	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
> +	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   
> +	ndelay(50);  // 50ns min delay needed as per HW design
>   	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
>   	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
>   
> +	msleep(30);  // 30ms delay needed as per HW design
> +	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
> +	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
>   	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
>   				 value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
>   				 500, 500 * 2000);


Reviewed-by: Jon Hunter <jonathanh@...dia.com>
Tested-by: Jon Hunter <jonathanh@...dia.com>

Thanks!
Jon

-- 
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