netdev - RE: [PATCH v3 net-next 12/13] net: enetc: add preliminary support for i.MX95 ENETC PF

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Message-ID:
 <PAXPR04MB8510E9F80DEAC6982D6D87A388412@PAXPR04MB8510.eurprd04.prod.outlook.com>
Date: Sat, 19 Oct 2024 10:22:02 +0000
From: Wei Fang <wei.fang@....com>
To: Frank Li <frank.li@....com>
CC: "davem@...emloft.net" <davem@...emloft.net>, "edumazet@...gle.com"
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Subject: RE: [PATCH v3 net-next 12/13] net: enetc: add preliminary support for
 i.MX95 ENETC PF

> > >
> > > [...]
> > > > > @@ -1721,14 +1724,25 @@ void enetc_get_si_caps(struct enetc_si
> *si)
> > > > >  	struct enetc_hw *hw = &si->hw;
> > > > >  	u32 val;
> > > > >
> > > > > +	if (is_enetc_rev1(si))
> > > > > +		si->clk_freq = ENETC_CLK;
> > > > > +	else
> > > > > +		si->clk_freq = ENETC_CLK_333M;
> > > >
> > > > can you use clk_gate_rate() to get frequency instead of hardcode here.
> > >
> > > clk_gate_rate() is not possible to be used here, enetc_get_si_caps()
> > > is shared by PF and VFs, but VF does not have DT node. Second,
> > > LS1028A and S32 platform do not use the clocks property.
> 
> It should be set when pf probe.
> 
> enetc4_pf_netdev_create()
> {
> 	...
> 	priv->ref_clk = devm_clk_get_optional(dev, "ref");
> 
> 	I am sure if it is "ref" clock.

si->clk_freq indicates the NETC system clock, not the ethernet reference
clock, and the system clock is not defined in fsl,enetc.yaml.

> 
> 	if (ref_clk)
> 		si->clk_freq = clk_get_rate(ref_clk);
> 	else
> 		si->clk_freq = ENETC_CLK; //default one for old LS1028A.

I still prefer the hardcode based on the IP revision, two reasons are as follows,
The first reason is that ENETC VF does not have a DT node, so VF cannot get
the system clock from DT.
The second reason is that S32 platform also not use the clocks property in DT,
so this solution is not suitable for S32 platform. In addition, for i.MX platforms,
there is a 1/2 divider inside the NETCMIX, the clock rate we get from clk_get_rate()
is 666MHz, and we need to divide by 2 to get the correct system clock rate. But
S32 does not have a NETCMIX so there may not have a 1/2 divider or may have
other dividers, even if it support the clocks property, the calculation of getting the
system clock rate is different. Therefore, the hardcode based on the IP revision is
simpler and clearer, and can be shared by both PF and VFs.

> 
> 	Next time, it may be become 444MHz, 555Mhz...
> }
>