[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <e0ad34dc-cc11-428e-8bf0-c764612452e0@app.fastmail.com>
Date: Mon, 18 Nov 2024 10:04:37 +0100
From: "Arnd Bergmann" <arnd@...db.de>
To: "Jacky Chou" <jacky_chou@...eedtech.com>,
"andrew+netdev@...n.ch" <andrew+netdev@...n.ch>,
"David S . Miller" <davem@...emloft.net>,
"Eric Dumazet" <edumazet@...gle.com>, "Jakub Kicinski" <kuba@...nel.org>,
"Paolo Abeni" <pabeni@...hat.com>, "Rob Herring" <robh@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"Conor Dooley" <conor+dt@...nel.org>,
"Philipp Zabel" <p.zabel@...gutronix.de>, Netdev <netdev@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [net-next v2 5/7] net: ftgmac100: add pin strap configuration for AST2700
On Mon, Nov 18, 2024, at 08:51, Jacky Chou wrote:
>> Is there a way to probe the presence of 64-bit addressing from hardware
>> registers? That would be nicer than triggering it from the compatible string,
>> given that any future SoC is likely also 64-bit.
I just realized I replied to the wrong email, I meant to send
my question as a reply to patch 4/7. The patch for the pin strap
looks fine.
> There is no register indicated about 64-bit address support in the
> ftgmac100 of Aspeed 7th generation. Therefore, we use the compatible
> to configure pin strap and DMA mask.
Later in the series you just unconditionally write the 64-bit
address, so it appears that the ftgmac100 can actually do
64-bti addressing all along, and this doesn't have to be
conditional at all, the call to dma_set_mask_and_coherent()
only tells the kernel that the device can do it, which should
work on all of them. Since the other devices won't have a
larger "dma-ranges" configuration in DT, and no RAM above
32-bit addressing, it should have no effect.
Just make that part in patch 5 unconditional.
Arnd
Powered by blists - more mailing lists