netdev - Re: [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt lines

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Message-ID: <72d06daa-82ed-4dc6-8396-fb20c63f5456@oss.nxp.com>
Date: Wed, 20 Nov 2024 12:47:02 +0200
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
To: Marc Kleine-Budde <mkl@...gutronix.de>
Cc: Vincent Mailhol <mailhol.vincent@...adoo.fr>,
 Andrew Lunn <andrew+netdev@...n.ch>, "David S . Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-can@...r.kernel.org,
 netdev@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, imx@...ts.linux.dev,
 NXP Linux Team <s32@....com>, Christophe Lizzi <clizzi@...hat.com>,
 Alberto Ruiz <aruizrui@...hat.com>, Enric Balletbo <eballetb@...hat.com>
Subject: Re: [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt
 lines

On 11/20/2024 12:29 PM, Marc Kleine-Budde wrote:
> On 20.11.2024 12:18:03, Ciprian Marian Costea wrote:
>> On 11/20/2024 12:01 PM, Marc Kleine-Budde wrote:
>>> On 20.11.2024 11:01:25, Ciprian Marian Costea wrote:
>>>> On 11/20/2024 10:52 AM, Marc Kleine-Budde wrote:
>>>>> On 19.11.2024 10:10:53, Ciprian Costea wrote:
>>>>>> From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
>>>>>>
>>>>>> On S32G2/S32G3 SoC, there are separate interrupts
>>>>>> for state change, bus errors, MBs 0-7 and MBs 8-127 respectively.
>>>>>>
>>>>>> In order to handle this FlexCAN hardware particularity, reuse
>>>>>> the 'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq
>>>>>> handling support.
>>>>>>
>>>>>> Additionally, introduce 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk,
>>>>>> which can be used in case there are two separate mailbox ranges
>>>>>> controlled by independent hardware interrupt lines, as it is
>>>>>> the case on S32G2/S32G3 SoC.
>>>>>
>>>>> Does the mainline driver already handle the 2nd mailbox range? Is there
>>>>> any downstream code yet?
>>>>>
>>>>> Marc
>>>>>
>>>>
>>>> Hello Marc,
>>>>
>>>> The mainline driver already handles the 2nd mailbox range (same
>>>> 'flexcan_irq') is used. The only difference is that for the 2nd mailbox
>>>> range a separate interrupt line is used.
>>>
>>> AFAICS the IP core supports up to 128 mailboxes, though the driver only
>>> supports 64 mailboxes. Which mailboxes do you mean by the "2nd mailbox
>>> range"? What about mailboxes 64..127, which IRQ will them?
>>
>> On S32G the following is the mapping between FlexCAN IRQs and mailboxes:
>> - IRQ line X -> Mailboxes 0-7
>> - IRQ line Y -> Mailboxes 8-127 (Logical OR of Message Buffer Interrupt
>> lines 127 to 8)
>>
>> By 2nd range, I was refering to Mailboxes 8-127.
> 
> Interesting, do you know why it's not symmetrical (0...63, 64...127)?
> Can you point me to the documentation.
> 
> Thanks,
> Marc
> 

Unfortunately I do not know why such hardware integration decisions have 
been made.

Documentation for S32G3 SoC can be found on the official NXP website, 
here: 
https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g3-processors-for-vehicle-networking:S32G3

But please note that you need to setup an account beforehand.

Best Regards,
Ciprian