netdev - Re: [PATCH net 2/4] ice: Fix quad registers read on E825

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Message-ID: <6f5b5241-2b08-4332-9268-fde890f0ae52@redhat.com>
Date: Tue, 10 Dec 2024 15:57:34 +0100
From: Paolo Abeni <pabeni@...hat.com>
To: Tony Nguyen <anthony.l.nguyen@...el.com>, davem@...emloft.net,
 kuba@...nel.org, edumazet@...gle.com, andrew+netdev@...n.ch,
 netdev@...r.kernel.org
Cc: Karol Kolacinski <karol.kolacinski@...el.com>, richardcochran@...il.com,
 przemyslaw.kitszel@...el.com, horms@...nel.org,
 Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
 Grzegorz Nitka <grzegorz.nitka@...el.com>,
 Pucha Himasekhar Reddy <himasekharx.reddy.pucha@...el.com>
Subject: Re: [PATCH net 2/4] ice: Fix quad registers read on E825

On 12/6/24 20:35, Tony Nguyen wrote:
> @@ -1988,50 +2045,48 @@ static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
>   */
>  int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
>  {
> -	u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
> -	u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1);
> +	u8 quad_lane = port % ICE_PORTS_PER_QUAD;
> +	u32 addr, val, peer_delay;
>  	bool enable, sfd_ena;
> -	u32 val, peer_delay;
>  	int err;
>  
>  	enable = hw->ptp.phy.eth56g.onestep_ena;
>  	peer_delay = hw->ptp.phy.eth56g.peer_delay;
>  	sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
>  
> -	/* PHY_PTP_1STEP_CONFIG */
> -	err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val);
> +	addr = PHY_PTP_1STEP_CONFIG;
> +	err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val);
>  	if (err)
>  		return err;
>  
>  	if (enable)
> -		val |= blk_port;
> +		val |= BIT(quad_lane);
>  	else
> -		val &= ~blk_port;
> +		val &= ~BIT(quad_lane);
>  
> -	val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
> +	val &= ~PHY_PTP_1STEP_T1S_UP64_M;
> +	val &= ~PHY_PTP_1STEP_T1S_DELTA_M;

Minor nit: please don't mix 'cosmetic' changes like the above one in a
fix, that makes the patch harder to read.

Thanks,

Paolo