lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID:
 <DM3PR11MB873610BA4FE0832FCB3CA5BAECE52@DM3PR11MB8736.namprd11.prod.outlook.com>
Date: Sat, 18 Jan 2025 04:07:40 +0000
From: <Tristram.Ha@...rochip.com>
To: <olteanv@...il.com>
CC: <andrew@...n.ch>, <maxime.chevallier@...tlin.com>,
	<Woojung.Huh@...rochip.com>, <davem@...emloft.net>, <edumazet@...gle.com>,
	<kuba@...nel.org>, <pabeni@...hat.com>, <UNGLinuxDriver@...rochip.com>,
	<netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net-next v2] net: dsa: microchip: Add SGMII port support
 to KSZ9477 switch

> On Sat, Jan 18, 2025 at 12:59:25AM +0000, Tristram.Ha@...rochip.com wrote:
> > Some of the register definitions are not present in the XPCS driver so I
> > need to add them.
> 
> Not a problem.
> 
> > Some register bits programmed by the XPCS driver do not have effect.
> 
> Like what?

Bit 9 (MAC_AUTO_SW) of 0x1f8000 is written in SGMII mode, but that bit
has no effect on KSZ9477, so it probably does not matter.

KSZ9477 does not need to update the 0x1f8000 register.

0x1f8001 needs to be written 0x18 in 1000BaseX mode, but the XPCS driver
does not do anything, and bit 4 is not defined in the driver.

The driver enables interrupt in 1000BaseX mode when poll is not set, but
it does not do that in SGMII Mode.  In KSZ9477 SGMII mode can trigger
both link up and link down interrupt, but 1000BaseX mode can only trigger
link up interrupt.  It requires polling to detect link down.


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ