netdev - Re: [PATCH net-next 3/4] net/mlx5: Modify LSB bitmask in temperature event to include only the first bit

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Message-ID: <c8ff6414-c7f1-4a0e-8318-62dd0506a52c@intel.com>
Date: Thu, 13 Feb 2025 13:11:15 +0100
From: Mateusz Polchlopek <mateusz.polchlopek@...el.com>
To: Tariq Toukan <tariqt@...dia.com>, "David S. Miller" <davem@...emloft.net>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, "Eric
 Dumazet" <edumazet@...gle.com>, Andrew Lunn <andrew+netdev@...n.ch>
CC: Shahar Shitrit <shshitrit@...dia.com>, Gal Pressman <gal@...dia.com>,
	Saeed Mahameed <saeedm@...dia.com>, Leon Romanovsky <leon@...nel.org>,
	<netdev@...r.kernel.org>, <linux-rdma@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net-next 3/4] net/mlx5: Modify LSB bitmask in temperature
 event to include only the first bit



On 2/13/2025 10:46 AM, Tariq Toukan wrote:
> From: Shahar Shitrit <shshitrit@...dia.com>
> 
> In the sensor_count field of the MTEWE register, bits 1-62 are
> supported only for unmanaged switches, not for NICs, and bit 63
> is reserved for internal use.
> 
> To prevent confusing output that may include set bits that are
> not relevant to NIC sensors, we update the bitmask to retain only
> the first bit, which corresponds to the sensor ASIC.
> 
> Signed-off-by: Shahar Shitrit <shshitrit@...dia.com>
> Signed-off-by: Tariq Toukan <tariqt@...dia.com>
> ---
>   drivers/net/ethernet/mellanox/mlx5/core/events.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/events.c b/drivers/net/ethernet/mellanox/mlx5/core/events.c
> index a661aa522a9a..e85a9042e3c2 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/events.c
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/events.c
> @@ -163,6 +163,10 @@ static int temp_warn(struct notifier_block *nb, unsigned long type, void *data)
>   	u64 value_msb;
>   
>   	value_lsb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb);
> +	/* bit 1-63 are not supported for NICs,
> +	 * hence read only bit 0 (asic) from lsb.
> +	 */
> +	value_lsb &= 0x1;
>   	value_msb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb);
>   
>   	if (net_ratelimit())

Reviewed-by: Mateusz Polchlopek <mateusz.polchlopek@...el.com>