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Message-ID: <20250214172150.0000136c@huawei.com>
Date: Fri, 14 Feb 2025 17:21:50 +0000
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: <alucerop@....com>
CC: <linux-cxl@...r.kernel.org>, <netdev@...r.kernel.org>,
<dan.j.williams@...el.com>, <edward.cree@....com>, <davem@...emloft.net>,
<kuba@...nel.org>, <pabeni@...hat.com>, <edumazet@...gle.com>,
<dave.jiang@...el.com>
Subject: Re: [PATCH v10 04/26] cxl: move register/capability check to driver
On Wed, 5 Feb 2025 15:19:28 +0000
alucerop@....com wrote:
> From: Alejandro Lucero <alucerop@....com>
>
> Type3 has some mandatory capabilities which are optional for Type2.
>
> In order to support same register/capability discovery code for both
> types, avoid any assumption about what capabilities should be there, and
> export the capabilities found for the caller doing the capabilities
> check based on the expected ones.
>
> Signed-off-by: Alejandro Lucero <alucerop@....com>
A few additional trivial comments.
With that and missing docs tidied up seems fine to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
>
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 722782b868ac..790d0520eaf4 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -5,6 +5,26 @@
> #define __CXL_H
>
> #include <linux/types.h>
> +
> +/* Capabilities as defined for:
Nit. It's not networking code, so lets use the standard
the rest of the kernel (more or less :) follows.
/*
* Capabilities as defined for:
> + *
> + * Component Registers (Table 8-22 CXL 3.1 specification)
> + * Device Registers (8.2.8.2.1 CXL 3.1 specification)
> + *
> + * and currently being used for kernel CXL support.
> + */
> +
> +enum cxl_dev_cap {
> + /* capabilities from Component Registers */
> + CXL_DEV_CAP_RAS,
> + CXL_DEV_CAP_HDM,
> + /* capabilities from Device Registers */
> + CXL_DEV_CAP_DEV_STATUS,
> + CXL_DEV_CAP_MAILBOX_PRIMARY,
> + CXL_DEV_CAP_MEMDEV,
> + CXL_MAX_CAPS,
> +};
> +
> /*
> * enum cxl_devtype - delineate type-2 from a generic type-3 device
> * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
> @@ -22,5 +42,4 @@ enum cxl_devtype {
> struct device;
> struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> u16 dvsec, enum cxl_devtype type);
> -
Stray change. Drop it or push to earlier patch so the line never existed.
> #endif
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