netdev - Re: [QUERY] : STMMAC Clocks

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Message-ID: <Z8Ms7C4-1IgjqBlq@shell.armlinux.org.uk>
Date: Sat, 1 Mar 2025 15:51:08 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>
Cc: "Lad, Prabhakar" <prabhakar.csengg@...il.com>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Giuseppe Cavallaro <peppe.cavallaro@...com>,
	Jose Abreu <joabreu@...opsys.com>, netdev <netdev@...r.kernel.org>
Subject: Re: [QUERY] : STMMAC Clocks

On Sat, Mar 01, 2025 at 04:15:17PM +0100, Andrew Lunn wrote:
> > However, I think that we should push to standardise on the Synopsys
> > named clock names where they exist (essentially optional) and then
> > allow platform specific clocks where they're buried out of view in
> > the way I describe above.
> 
> Interestingly snps,dwc-qos-ethernet.txt has a pretty good description:
> 
> - clock-names: May contain any/all of the following depending on the IP
>   configuration, in any order:
>   - "tx"
>     The EQOS transmit path clock. The HW signal name is clk_tx_i.
>     In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
>     path. In other configurations, other clocks (such as tx_125, rmii) may
>     drive the PHY TX path.
>   - "rx"
>     The EQOS receive path clock. The HW signal name is clk_rx_i.
>     In some configurations (e.g. GMII/RGMII), this clock is derived from the
>     PHY's RX clock output. In other configurations, other clocks (such as
>     rx_125, rmii) may drive the EQOS RX path.
>     In cases where the PHY clock is directly fed into the EQOS receive path
>     without intervening logic, the DT need not represent this clock, since it
>     is assumed to be fully under the control of the PHY device/driver. In
>     cases where SoC integration adds additional logic to this path, such as a
>     SW-controlled clock gate, this clock should be represented in DT.
>   - "slave_bus"
>     The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
>     APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
>     buses).
>   - "master_bus"
>     The master bus interface clock. Only required in configurations that use a
>     separate clock for the master and slave bus interfaces. The HW signal name
>     is hclk_i (AHB) or aclk_i (AXI).
>   - "ptp_ref"
>     The PTP reference clock. The HW signal name is clk_ptp_ref_i.
>   - "phy_ref_clk"
>     This clock is deprecated and should not be used by new compatible values.
>     It is equivalent to "tx".
>   - "apb_pclk"
>     This clock is deprecated and should not be used by new compatible values.
>     It is equivalent to "slave_bus".
> 
> But snps,dwmac.yaml only has:
> 
>  clock-names:
>     minItems: 1
>     maxItems: 8
>     additionalItems: true
>     contains:
>       enum:
>         - stmmaceth
>         - pclk
>         - ptp_ref
> 
> Could you improve the description in snps,dwmac.yaml, based on what
> you seen in the data book?

I'm afraid I can't, because the description there is basically rubbish.
As I stated in my previous email, the only one listed there which
means anything as far as the databook is concerned is "ptp_ref". The
other two are just made up names that have no basis for anything in
the databook.

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