netdev - Re: [PATCH iwl-next v2 3/3] ice: enable timesync operation on 2xNAC E825 devices

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Message-ID: <20250317163634.GE688833@kernel.org>
Date: Mon, 17 Mar 2025 16:36:34 +0000
From: Simon Horman <horms@...nel.org>
To: Grzegorz Nitka <grzegorz.nitka@...el.com>
Cc: intel-wired-lan@...ts.osuosl.org, netdev@...r.kernel.org,
	Karol Kolacinski <karol.kolacinski@...el.com>,
	Przemek Kitszel <przemyslaw.kitszel@...el.com>
Subject: Re: [PATCH iwl-next v2 3/3] ice: enable timesync operation on 2xNAC
 E825 devices

On Mon, Mar 10, 2025 at 01:24:39PM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski <karol.kolacinski@...el.com>
> 
> According to the E825C specification, SBQ address for ports on a single
> complex is device 2 for PHY 0 and device 13 for PHY1.
> For accessing ports on a dual complex E825C (so called 2xNAC mode),
> the driver should use destination device 2 (referred as phy_0) for
> the current complex PHY and device 13 (referred as phy_0_peer) for
> peer complex PHY.
> 
> Differentiate SBQ destination device by checking if current PF port
> number is on the same PHY as target port number.
> 
> Adjust 'ice_get_lane_number' function to provide unique port number for
> ports from PHY1 in 'dual' mode config (by adding fixed offset for PHY1
> ports). Cache this value in ice_hw struct.
> 
> Introduce ice_get_primary_hw wrapper to get access to timesync register
> not available from second NAC.
> 
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@...el.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Co-developed-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>

Reviewed-by: Simon Horman <horms@...nel.org>