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Message-ID: <202504160058.DWk5ApNJ-lkp@intel.com>
Date: Wed, 16 Apr 2025 01:19:16 +0800
From: kernel test robot <lkp@...el.com>
To: alejandro.lucero-palau@....com, linux-cxl@...r.kernel.org,
netdev@...r.kernel.org, dan.j.williams@...el.com,
edward.cree@....com, davem@...emloft.net, kuba@...nel.org,
pabeni@...hat.com, edumazet@...gle.com, dave.jiang@...el.com
Cc: oe-kbuild-all@...ts.linux.dev, Alejandro Lucero <alucerop@....com>,
Ben Cheatham <benjamin.cheatham@....com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>
Subject: Re: [PATCH v13 13/22] cxl: define a driver interface for DPA
allocation
Hi,
kernel test robot noticed the following build errors:
[auto build test ERROR on 73c117c17b562213242f432db2ddf1bcc22f39dd]
url: https://github.com/intel-lab-lkp/linux/commits/alejandro-lucero-palau-amd-com/cxl-add-type2-device-basic-support/20250414-233241
base: 73c117c17b562213242f432db2ddf1bcc22f39dd
patch link: https://lore.kernel.org/r/20250414151336.3852990-14-alejandro.lucero-palau%40amd.com
patch subject: [PATCH v13 13/22] cxl: define a driver interface for DPA allocation
config: csky-randconfig-002-20250415
compiler: csky-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build):
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504160058.DWk5ApNJ-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/cxl/core/hdm.c:6:
>> include/cxl/cxl.h:153:22: error: field 'dpa_range' has incomplete type
153 | struct range dpa_range;
| ^~~~~~~~~
>> include/cxl/cxl.h:227:30: error: field 'range' has incomplete type
227 | struct range range;
| ^~~~~
vim +/dpa_range +153 include/cxl/cxl.h
04ccf61aaf26953 Alejandro Lucero 2025-04-14 144
04ccf61aaf26953 Alejandro Lucero 2025-04-14 145 /**
04ccf61aaf26953 Alejandro Lucero 2025-04-14 146 * struct cxl_dpa_perf - DPA performance property entry
04ccf61aaf26953 Alejandro Lucero 2025-04-14 147 * @dpa_range: range for DPA address
04ccf61aaf26953 Alejandro Lucero 2025-04-14 148 * @coord: QoS performance data (i.e. latency, bandwidth)
04ccf61aaf26953 Alejandro Lucero 2025-04-14 149 * @cdat_coord: raw QoS performance data from CDAT
04ccf61aaf26953 Alejandro Lucero 2025-04-14 150 * @qos_class: QoS Class cookies
04ccf61aaf26953 Alejandro Lucero 2025-04-14 151 */
04ccf61aaf26953 Alejandro Lucero 2025-04-14 152 struct cxl_dpa_perf {
04ccf61aaf26953 Alejandro Lucero 2025-04-14 @153 struct range dpa_range;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 154 struct access_coordinate coord[ACCESS_COORDINATE_MAX];
04ccf61aaf26953 Alejandro Lucero 2025-04-14 155 struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
04ccf61aaf26953 Alejandro Lucero 2025-04-14 156 int qos_class;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 157 };
04ccf61aaf26953 Alejandro Lucero 2025-04-14 158
04ccf61aaf26953 Alejandro Lucero 2025-04-14 159 enum cxl_partition_mode {
04ccf61aaf26953 Alejandro Lucero 2025-04-14 160 CXL_PARTMODE_RAM,
04ccf61aaf26953 Alejandro Lucero 2025-04-14 161 CXL_PARTMODE_PMEM,
04ccf61aaf26953 Alejandro Lucero 2025-04-14 162 };
04ccf61aaf26953 Alejandro Lucero 2025-04-14 163
04ccf61aaf26953 Alejandro Lucero 2025-04-14 164 /**
04ccf61aaf26953 Alejandro Lucero 2025-04-14 165 * struct cxl_dpa_partition - DPA partition descriptor
04ccf61aaf26953 Alejandro Lucero 2025-04-14 166 * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
04ccf61aaf26953 Alejandro Lucero 2025-04-14 167 * @perf: performance attributes of the partition from CDAT
04ccf61aaf26953 Alejandro Lucero 2025-04-14 168 * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
04ccf61aaf26953 Alejandro Lucero 2025-04-14 169 */
04ccf61aaf26953 Alejandro Lucero 2025-04-14 170 struct cxl_dpa_partition {
04ccf61aaf26953 Alejandro Lucero 2025-04-14 171 struct resource res;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 172 struct cxl_dpa_perf perf;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 173 enum cxl_partition_mode mode;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 174 };
04ccf61aaf26953 Alejandro Lucero 2025-04-14 175
04ccf61aaf26953 Alejandro Lucero 2025-04-14 176 #define CXL_NR_PARTITIONS_MAX 2
04ccf61aaf26953 Alejandro Lucero 2025-04-14 177
04ccf61aaf26953 Alejandro Lucero 2025-04-14 178 /**
04ccf61aaf26953 Alejandro Lucero 2025-04-14 179 * struct cxl_dev_state - The driver device state
04ccf61aaf26953 Alejandro Lucero 2025-04-14 180 *
04ccf61aaf26953 Alejandro Lucero 2025-04-14 181 * cxl_dev_state represents the CXL driver/device state. It provides an
04ccf61aaf26953 Alejandro Lucero 2025-04-14 182 * interface to mailbox commands as well as some cached data about the device.
04ccf61aaf26953 Alejandro Lucero 2025-04-14 183 * Currently only memory devices are represented.
04ccf61aaf26953 Alejandro Lucero 2025-04-14 184 *
04ccf61aaf26953 Alejandro Lucero 2025-04-14 185 * @dev: The device associated with this CXL state
04ccf61aaf26953 Alejandro Lucero 2025-04-14 186 * @cxlmd: The device representing the CXL.mem capabilities of @dev
04ccf61aaf26953 Alejandro Lucero 2025-04-14 187 * @reg_map: component and ras register mapping parameters
04ccf61aaf26953 Alejandro Lucero 2025-04-14 188 * @regs: Parsed register blocks
04ccf61aaf26953 Alejandro Lucero 2025-04-14 189 * @cxl_dvsec: Offset to the PCIe device DVSEC
04ccf61aaf26953 Alejandro Lucero 2025-04-14 190 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
04ccf61aaf26953 Alejandro Lucero 2025-04-14 191 * @media_ready: Indicate whether the device media is usable
04ccf61aaf26953 Alejandro Lucero 2025-04-14 192 * @dpa_res: Overall DPA resource tree for the device
04ccf61aaf26953 Alejandro Lucero 2025-04-14 193 * @part: DPA partition array
04ccf61aaf26953 Alejandro Lucero 2025-04-14 194 * @nr_partitions: Number of DPA partitions
04ccf61aaf26953 Alejandro Lucero 2025-04-14 195 * @serial: PCIe Device Serial Number
04ccf61aaf26953 Alejandro Lucero 2025-04-14 196 * @type: Generic Memory Class device or Vendor Specific Memory device
04ccf61aaf26953 Alejandro Lucero 2025-04-14 197 * @cxl_mbox: CXL mailbox context
04ccf61aaf26953 Alejandro Lucero 2025-04-14 198 * @cxlfs: CXL features context
04ccf61aaf26953 Alejandro Lucero 2025-04-14 199 */
04ccf61aaf26953 Alejandro Lucero 2025-04-14 200 struct cxl_dev_state {
04ccf61aaf26953 Alejandro Lucero 2025-04-14 201 /* public for Type2 drivers */
04ccf61aaf26953 Alejandro Lucero 2025-04-14 202 struct device *dev;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 203 struct cxl_memdev *cxlmd;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 204
04ccf61aaf26953 Alejandro Lucero 2025-04-14 205 /* private for Type2 drivers */
04ccf61aaf26953 Alejandro Lucero 2025-04-14 206 struct cxl_register_map reg_map;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 207 struct cxl_regs regs;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 208 int cxl_dvsec;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 209 bool rcd;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 210 bool media_ready;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 211 struct resource dpa_res;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 212 struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
04ccf61aaf26953 Alejandro Lucero 2025-04-14 213 unsigned int nr_partitions;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 214 u64 serial;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 215 enum cxl_devtype type;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 216 struct cxl_mailbox cxl_mbox;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 217 #ifdef CONFIG_CXL_FEATURES
04ccf61aaf26953 Alejandro Lucero 2025-04-14 218 struct cxl_features_state *cxlfs;
04ccf61aaf26953 Alejandro Lucero 2025-04-14 219 #endif
04ccf61aaf26953 Alejandro Lucero 2025-04-14 220 };
04ccf61aaf26953 Alejandro Lucero 2025-04-14 221
dd50535762e809d Alejandro Lucero 2025-04-14 222 #define CXL_NR_PARTITIONS_MAX 2
dd50535762e809d Alejandro Lucero 2025-04-14 223
dd50535762e809d Alejandro Lucero 2025-04-14 224 struct cxl_dpa_info {
dd50535762e809d Alejandro Lucero 2025-04-14 225 u64 size;
dd50535762e809d Alejandro Lucero 2025-04-14 226 struct cxl_dpa_part_info {
dd50535762e809d Alejandro Lucero 2025-04-14 @227 struct range range;
dd50535762e809d Alejandro Lucero 2025-04-14 228 enum cxl_partition_mode mode;
dd50535762e809d Alejandro Lucero 2025-04-14 229 } part[CXL_NR_PARTITIONS_MAX];
dd50535762e809d Alejandro Lucero 2025-04-14 230 int nr_partitions;
dd50535762e809d Alejandro Lucero 2025-04-14 231 };
dd50535762e809d Alejandro Lucero 2025-04-14 232
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
View attachment "reproduce" of type "text/plain" (614 bytes)
View attachment "config" of type "text/plain" (123539 bytes)
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