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Message-ID: <682e1fc963402_1626e1001c@dwillia2-xfh.jf.intel.com.notmuch>
Date: Wed, 21 May 2025 11:47:37 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: <alejandro.lucero-palau@....com>, <linux-cxl@...r.kernel.org>,
<netdev@...r.kernel.org>, <dan.j.williams@...el.com>, <edward.cree@....com>,
<davem@...emloft.net>, <kuba@...nel.org>, <pabeni@...hat.com>,
<edumazet@...gle.com>, <dave.jiang@...el.com>
CC: Alejandro Lucero <alucerop@....com>, Ben Cheatham
<benjamin.cheatham@....com>, Jonathan Cameron <Jonathan.Cameron@...wei.com>
Subject: Re: [PATCH v16 07/22] cxl: Support dpa initialization without a
mailbox
alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@....com>
>
> Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing
> memdev state params which end up being used for DMA initialization.
>
> Allow a Type2 driver to initialize DPA simply by giving the size of its
> volatile and/or non-volatile hardware partitions.
>
> Export cxl_dpa_setup as well for initializing those added DPA partitions
> with the proper resources.
>
> Signed-off-by: Alejandro Lucero <alucerop@....com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> ---
> drivers/cxl/core/mbox.c | 26 ++++++++++++++++++++------
> drivers/cxl/cxlmem.h | 13 -------------
> include/cxl/cxl.h | 14 ++++++++++++++
> 3 files changed, 34 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index ab994d459f46..b14cfc6e3dba 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1284,6 +1284,22 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa
> info->nr_partitions++;
> }
>
> +/**
> + * cxl_mem_dpa_init: initialize dpa by a driver without a mailbox.
> + *
> + * @info: pointer to cxl_dpa_info
> + * @volatile_bytes: device volatile memory size
> + * @persistent_bytes: device persistent memory size
> + */
> +void cxl_mem_dpa_init(struct cxl_dpa_info *info, u64 volatile_bytes,
> + u64 persistent_bytes)
I struggle to imagine a Type-2 device with PMEM, or needing anything
more complicated than a single volatile range. No need to pre-enable
something that may never exist.
Lets just have a cxl_set_capacity() for the simple / common case:
int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity)
{
struct cxl_dpa_info range_info = { 0 };
add_part(info, 0, capacity, CXL_PARTMODE_RAM);
return cxl_dpa_setup(cxlds, &range_info);
}
...then there is no need to move 'struct cxl_dpa_info' to a public
header, or require type-2 drivers to pass in a pointless PMEM capacity.
If more complicated devices show up later the code can always be made
more sophisticated at that point.
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