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Message-ID: <0444ceee9743a349bb7155dac6ca7ea25f5adb18.camel@pengutronix.de>
Date: Mon, 16 Jun 2025 13:01:34 +0200
From: Philipp Zabel <p.zabel@...gutronix.de>
To: george.moussalem@...look.com, Andrew Lunn <andrew@...n.ch>, Heiner
Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet
<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
<pabeni@...hat.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Florian Fainelli
<f.fainelli@...il.com>, Bjorn Andersson <andersson@...nel.org>, Konrad
Dybcio <konradybcio@...nel.org>, Michael Turquette
<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018
Internal PHY support
On Mo, 2025-06-02 at 13:53 +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@...look.com>
>
> The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which
> provides an MDI interface directly to an RJ45 connector or an external
> switch over a PHY to PHY link.
>
> The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
> 802.3az EEE.
>
> Let's add support for this PHY in the at803x driver as it falls within
> the Qualcomm Atheros OUI.
>
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
> drivers/net/phy/qcom/Kconfig | 2 +-
> drivers/net/phy/qcom/at803x.c | 185 ++++++++++++++++++++++++++++++++++++++++--
> 2 files changed, 178 insertions(+), 9 deletions(-)
>
[...]
> diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c
> index 26350b962890b0321153d74758b13d817407d094..c148e245b5391c5da374ace8609dcdfd8284732d 100644
> --- a/drivers/net/phy/qcom/at803x.c
> +++ b/drivers/net/phy/qcom/at803x.c
> @@ -7,19 +7,24 @@
[...]
> +static int ipq5018_probe(struct phy_device *phydev)
> +{
> + struct device *dev = &phydev->mdio.dev;
> + struct ipq5018_priv *priv;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
> + "qcom,dac-preset-short-cable");
> +
> + priv->rst = devm_reset_control_array_get_exclusive(dev);
Both dt-bindings and dts patch only show a single reset. Is there a
reason this is a reset_control_array?
regards
Philipp
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