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Message-ID: <CA+V-a8uizu5MCur_=g5vJyWbWSTSP2J6FkQ89JB8ges7GWdsjg@mail.gmail.com>
Date: Thu, 19 Jun 2025 09:59:41 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: John Madieu <john.madieu.xa@...renesas.com>
Cc: andrew+netdev@...n.ch, conor+dt@...nel.org, davem@...emloft.net,
edumazet@...gle.com, geert+renesas@...der.be, krzk+dt@...nel.org,
kuba@...nel.org, pabeni@...hat.com, prabhakar.mahadev-lad.rj@...renesas.com,
robh@...nel.org, biju.das.jz@...renesas.com, devicetree@...r.kernel.org,
john.madieu@...il.com, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, magnus.damm@...il.com,
netdev@...r.kernel.org
Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable
eth{0-1} (GBETH) interfaces
Hi John,
Thank you for the patch.
On Wed, Jun 11, 2025 at 7:20 AM John Madieu
<john.madieu.xa@...renesas.com> wrote:
>
> Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
>
> Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
> Tested-by: Biju Das <biju.das.jz@...renesas.com>
> Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
> ---
> .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 106 ++++++++++++++++++
> 1 file changed, 106 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> index f99a09d04ddd..4b4c7f3381ad 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> @@ -26,6 +26,8 @@ / {
> compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
>
> aliases {
> + ethernet0 = ð0;
> + ethernet1 = ð1;
> i2c2 = &i2c2;
> mmc0 = &sdhi0;
> mmc2 = &sdhi2;
> @@ -77,6 +79,74 @@ &audio_extal_clk {
> clock-frequency = <48000000>;
> };
>
> +ð0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> +
> + pinctrl-0 = <ð0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy0: ethernet-phy@7 {
> + compatible = "ethernet-phy-id0022.1640",
> + "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
> + rxc-skew-psec = <1400>;
> + txc-skew-psec = <1400>;
> + rxdv-skew-psec = <0>;
> + txdv-skew-psec = <0>;
> + rxd0-skew-psec = <0>;
> + rxd1-skew-psec = <0>;
> + rxd2-skew-psec = <0>;
> + rxd3-skew-psec = <0>;
> + txd0-skew-psec = <0>;
> + txd1-skew-psec = <0>;
> + txd2-skew-psec = <0>;
> + txd3-skew-psec = <0>;
> + };
> + };
> +};
> +
> +ð1 {
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> +
> + pinctrl-0 = <ð1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy1: ethernet-phy@7 {
> + compatible = "ethernet-phy-id0022.1640",
> + "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
> + rxc-skew-psec = <1400>;
> + txc-skew-psec = <1400>;
> + rxdv-skew-psec = <0>;
> + txdv-skew-psec = <0>;
> + rxd0-skew-psec = <0>;
> + rxd1-skew-psec = <0>;
> + rxd2-skew-psec = <0>;
> + rxd3-skew-psec = <0>;
> + txd0-skew-psec = <0>;
> + txd1-skew-psec = <0>;
> + txd2-skew-psec = <0>;
> + txd3-skew-psec = <0>;
> + };
> + };
> +};
> +
> &gpu {
> status = "okay";
> mali-supply = <®_vdd0p8v_others>;
> @@ -103,6 +173,42 @@ raa215300: pmic@12 {
> };
>
> &pinctrl {
> + eth0_pins: eth0 {
> + pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
> + <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> + <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
> + <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> + <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> + <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> + <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> + <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
> + <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> + <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> + <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> + <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> + <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> + <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
> + <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
like RZ/V2H on RZ/G3E PFC_OEN BITS(0,1) need to be configured based on
RGMII/MII mode?
Cheers,
Prabhakar
> + };
> +
> + eth1_pins: eth1 {
> + pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
> + <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
> + <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
> + <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
> + <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
> + <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
> + <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
> + <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
> + <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
> + <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
> + <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
> + <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
> + <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
> + <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
> + <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
> + };
> +
> i2c2_pins: i2c {
> pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
> <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
> --
> 2.25.1
>
>
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