netdev - RE: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

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Message-ID:
 <OSCPR01MB14647AB8B2901DE1EBEB32145FF46A@OSCPR01MB14647.jpnprd01.prod.outlook.com>
Date: Mon, 30 Jun 2025 16:22:56 +0000
From: John Madieu <john.madieu.xa@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
CC: "andrew+netdev@...n.ch" <andrew+netdev@...n.ch>, "conor+dt@...nel.org"
	<conor+dt@...nel.org>, "davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "kuba@...nel.org" <kuba@...nel.org>,
	"pabeni@...hat.com" <pabeni@...hat.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>, "robh@...nel.org"
	<robh@...nel.org>, Biju Das <biju.das.jz@...renesas.com>, "Lad, Prabhakar"
	<prabhakar.csengg@...il.com>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "john.madieu@...il.com"
	<john.madieu@...il.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>, "magnus.damm@...il.com"
	<magnus.damm@...il.com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
 signals for the GBETH IPs

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: Wednesday, June 25, 2025 5:19 PM
> To: John Madieu <john.madieu.xa@...renesas.com>
> Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
> 
> Ho John,
> 
> On Thu, 19 Jun 2025 at 10:22, Lad, Prabhakar <prabhakar.csengg@...il.com>
> wrote:
> > On Thu, Jun 19, 2025 at 5:34 AM John Madieu
> > <john.madieu.xa@...renesas.com> wrote:
> > > > From: Geert Uytterhoeven <geert@...ux-m68k.org> On Wed, 18 Jun
> > > > 2025 at 12:04, John Madieu <john.madieu.xa@...renesas.com>
> > > > wrote:
> > > > > > From: Geert Uytterhoeven <geert@...ux-m68k.org> On Wed, 11 Jun
> > > > > > 2025 at 11:02, John Madieu <john.madieu.xa@...renesas.com>
> > > > > > wrote:
> > > > > > > Add clock and reset entries for the Gigabit Ethernet
> > > > > > > Interfaces (GBETH
> > > > > > > 0-1) IPs found on the RZ/G3E SoC. This includes various
> > > > > > > PLLs, dividers, and mux clocks needed by these two GBETH IPs.
> > > > > > >
> > > > > > > Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
> > > > > > > Tested-by: Biju Das <biju.das.jz@...renesas.com>
> > > > > > > Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > > >
> >
> > "The clock gating cells require source clocks to operate correctly. If
> > the source clocks are stopped, these registers cannot be used."
> 
> Has this been sorted out yet? I see no change or mention of it in v3.
> 

Yes, it has been sorted out. I mean they operated properly after
all the tests, even after S2R/wakeup test.

While at it, even with OEN patches applied, I could not reproduce
the issue known to V2H. That's why I've asked if you'd prefer
DEF_MOD_EXTERNAL instead of DEF_MOD (which does not work on V2H)
for consistency with RZ/V2H, I can do that as well.

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

Regards,
John

> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds