netdev - Re: [PATCH net] net: phy: realtek: Reset after clock enable

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <5xjp2k3b4rggbmjgchg6vlusotoqoqmxi54zzer3ioxv274vtx@22tzjjcs7s3z>
Date: Fri, 4 Jul 2025 22:35:00 +0200
From: Sebastian Reichel <sebastian.reichel@...labora.com>
To: Heiner Kallweit <hkallweit1@...il.com>, 
	Detlev Casanova <detlev.casanova@...labora.com>
Cc: Andrew Lunn <andrew@...n.ch>, Russell King <linux@...linux.org.uk>, 
	"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Florian Fainelli <florian.fainelli@...adcom.com>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, 
	stable@...r.kernel.org, kernel@...labora.com
Subject: Re: [PATCH net] net: phy: realtek: Reset after clock enable

Hi,

On Fri, Jul 04, 2025 at 10:18:29PM +0200, Heiner Kallweit wrote:
> On 04.07.2025 19:48, Sebastian Reichel wrote:
> > On Radxa ROCK 4D boards we are seeing some issues with PHY detection and
> > stability (e.g. link loss, or not capable of transceiving packages)
> > after new board revisions switched from a dedicated crystal to providing
> > the 25 MHz PHY input clock from the SoC instead.
> > 
> > This board is using a RTL8211F PHY, which is connected to an always-on
> > regulator. Unfortunately the datasheet does not explicitly mention the
> > power-up sequence regarding the clock, but it seems to assume that the
> > clock is always-on (i.e. dedicated crystal).
> > 
> > By doing an explicit reset after enabling the clock, the issue on the
> > boards could no longer be observed.
> > 
> Is the SoC clock always on after boot? Or may it be disabled e.g.
> during system suspend? Then you would have to do the PHY reset also
> on resume from suspend.

Upstream kernel does not yet support suspend/resume on Rockchip RK3576
(the SoC used by the ROCK 4D) and I missed, that the clock is disabled
in the PHY's suspend routine.

Detlev: You added the initial clock support to the driver. If I add
the reset in the resume routine, can you do regression testing on
the board you originally added the clock handling for?

Greetings,

-- Sebastian

> > Cc: stable@...r.kernel.org
> > Fixes: 7300c9b574cc ("net: phy: realtek: Add optional external PHY clock")
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
> > ---
> >  drivers/net/phy/realtek/realtek_main.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
> > index c3dcb62574303374666b46a454cd4e10de455d24..3a783f0c3b4f2a4f6aa63a16ad309e3471b0932a 100644
> > --- a/drivers/net/phy/realtek/realtek_main.c
> > +++ b/drivers/net/phy/realtek/realtek_main.c
> > @@ -231,6 +231,10 @@ static int rtl821x_probe(struct phy_device *phydev)
> >  		return dev_err_probe(dev, PTR_ERR(priv->clk),
> >  				     "failed to get phy clock\n");
> >  
> > +	/* enabling the clock might produce glitches, so hard-reset the PHY */
> > +	phy_device_reset(phydev, 1);
> > +	phy_device_reset(phydev, 0);
> > +
> >  	ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1);
> >  	if (ret < 0)
> >  		return ret;
> > 
> > ---
> > base-commit: 4c06e63b92038fadb566b652ec3ec04e228931e8
> > change-id: 20250704-phy-realtek-clock-fix-6cd393e8cb2a
> > 
> > Best regards,
> 

Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)